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/* SPDX-License-Identifier: GPL-2.0
* Marvell OcteonTx2 RVU Admin Function driver
*
* Copyright (C) 2018 Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef RVU_H
#define RVU_H
#include "rvu_struct.h"
/* PCI device IDs */
#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
/* PCI BAR nos */
#define PCI_AF_REG_BAR_NUM 0
#define PCI_PF_REG_BAR_NUM 2
#define PCI_MBOX_BAR_NUM 4
#define NAME_SIZE 32
struct rvu_block {
bool implemented;
};
struct rvu_hwinfo {
struct rvu_block block[BLK_COUNT]; /* Block info */
};
struct rvu {
void __iomem *afreg_base;
void __iomem *pfreg_base;
struct pci_dev *pdev;
struct device *dev;
struct rvu_hwinfo *hw;
};
static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
{
writeq(val, rvu->afreg_base + ((block << 28) | offset));
}
static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
{
return readq(rvu->afreg_base + ((block << 28) | offset));
}
static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
{
writeq(val, rvu->pfreg_base + offset);
}
static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
{
return readq(rvu->pfreg_base + offset);
}
/* Function Prototypes
* RVU
*/
int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
#endif /* RVU_H */
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