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path: root/arch/arc/mm/tlb.c (follow)
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2013-11-06ARC: [SMP] TLB flushVineet Gupta1-0/+73
2013-11-06ARC: [SMP] ASID allocationVineet Gupta1-6/+8
2013-11-06ARC: Fix bogus gcc warning and micro-optimise TLB iteration loopVineet Gupta1-2/+2
2013-08-30ARC: [ASID] Track ASID allocation cycles/generationsVineet Gupta1-15/+7
2013-08-30ARC: [ASID] get_new_mmu_context() to conditionally allocate new ASIDVineet Gupta1-6/+7
2013-08-30ARC: [ASID] Refactor the TLB paranoid debug codeVineet Gupta1-11/+13
2013-08-30ARC: No need to flush the TLB in early bootVineet Gupta1-7/+0
2013-08-30ARC: MMUv4 preps/3 - Abstract out TLB Insert/DeleteVineet Gupta1-40/+54
2013-08-30ARC: MMUv4 preps/2 - Reshuffle PTE bitsVineet Gupta1-8/+3
2013-08-29ARC: MMUv4 preps/1 - Fold PTE K/U access flagsVineet Gupta1-2/+17
2013-06-27arc: delete __cpuinit usage from all arc filesPaul Gortmaker1-2/+2
2013-06-22ARC: [mm] Assume pagecache page dirty by defaultVineet Gupta1-1/+1
2013-06-22ARC: [mm] Zero page optimizationVineet Gupta1-1/+5
2013-06-22ARC: Disintegrate arcregs.hVineet Gupta1-4/+20
2013-06-22ARC: Use kconfig helper IS_ENABLED() to get rid of defines.hVineet Gupta1-1/+1
2013-05-23ARC: Brown paper bag bug in macro for checking cache colorVineet Gupta1-1/+2
2013-05-09ARC: [mm] Aliasing VIPT dcache support 2/4Vineet Gupta1-6/+21
2013-05-09ARC: [mm] Aliasing VIPT dcache support 1/4Vineet Gupta1-1/+1
2013-05-07ARC: [mm] Lazy D-cache flush (non aliasing VIPT)Vineet Gupta1-5/+13
2013-05-07ARC: [mm] optimise icache flush for user mappingsVineet Gupta1-3/+9
2013-05-07ARC: Respect the cpu_id passed for fetching correct cpu infoNoam Camus1-1/+1
2013-04-09ARC: [build] Fix warnings with CONFIG_DEBUG_SECTION_MISMATCHVineet Gupta1-2/+2
2013-02-15ARC: Boot #2: Verbose Boot reporting / feature verificationVineet Gupta1-0/+38
2013-02-15ARC: SMP supportVineet Gupta1-0/+6
2013-02-15ARC: TLB flush HandlingVineet Gupta1-0/+311
2013-02-15ARC: MMU Exception HandlingVineet Gupta1-0/+267
2013-02-15ARC: MMU Context ManagementVineet Gupta1-0/+23
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