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2021-09-28ARM: dts: renesas: Add compatible properties to LAN8710A Ethernet PHYsGeert Uytterhoeven1-0/+2
Add compatible values to Ethernet PHY subnodes representing SMSC LAN8710A PHYs on RZ/A1 and R-Mobile A1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/247dc2074dae149af07b6d014985ad30eb362eda.1631174218.git.geert+renesas@glider.be
2020-02-10ARM: dts: r7s72100: Add SPIBSC clocksChris Brandt1-0/+3
Add clocks for SPIBSC blocks. Also modify the flash node for the GR-PEACH board at the same time because now that the SPIBSC clock is identified, if it is not used by any driver, it will be turned off at the end of kernel boot. That would not work out so well for an XIP system such as GR-PEACH. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Link: https://lore.kernel.org/r/20200210123153.8257-1-chris.brandt@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-07-23ARM: dts: convert to SPDX identifier for Renesas boardsWolfram Sang1-4/+1
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: gr-peach: Enable ostm0 and ostm1 timersJacopo Mondi1-0/+8
Enable ostm0 and ostm1 timers to be used as clock source and clockevent source. The timers provides greater accuracy than the already enabled mtu2 one. With these enabled: clocksource: ostm: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 57352151442 ns sched_clock: 32 bits at 33MHz, resolution 30ns, wraps every 64440619504ns ostm: used for clocksource ostm: used for clock events Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Suggested-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: gr-peach: Add ETHER pin groupJacopo Mondi1-0/+39
Add pin configuration subnode for ETHER pin group. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-05ARM: dts: gr-peach: Enable MTU2 timer pulse unitJacopo Mondi1-0/+4
MTU2 multi-function/multi-channel timer/counter is not enabled for GR-Peach board. The timer is used as clock event source to schedule wake-ups, and without this enabled all sleeps not performed through busy waiting hang the board. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-05ARM: dts: gr-peach: Fix 'leds' node name indentJacopo Mondi1-1/+1
Fix 'leds' node name indent as it was wrongly aligned. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: gr-peach: Add user led device nodesJacopo Mondi1-0/+10
Add device nodes for user leds on gr-peach board. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: gr-peach: Add SCIF2 pin groupJacopo Mondi1-0/+11
Add pin configuration subnode for SCIF2 serial debug interface. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: gr-peach: Remove empty lineJacopo Mondi1-1/+0
Remove an empty line in gr-peach device tree source file. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-06-12ARM: dts: r7s72100: Add support for GR-PeachJacopo Mondi1-0/+66
Add device tree source for Renesas GR-Peach board. GR-Peach is an RZ/A1H based board with 10MB of on-chip SRAM and 8MB QSPI flash storage. Add support for the board, and create a 2MB partition to use as rootfs. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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