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To inject the error using the tmr inject IP reset vectors need to be placed
in lmb(bram) due to the limitation in HW when this code runs out of DDR.
Below code adds the error inject code to the .init.ivt section to copy
it in machine_early_init to lmb/Bram location. C_BASE_VECTORS which allow
moving reset vectors out of 0 location is not currently supported by
Microblaze architecture, that's why all the time reset vectors with
injection code is all the time copied to address 0.
As of now getting this functionality working CPU switches to real mode
and simply jumps to bram, which causes triggering of fault which continues
to call_xmb_manager_break break handler which will at the end calls the
error count callback function and performs recovery.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Link: https://lore.kernel.org/r/20220627064024.771037-4-appana.durga.rao@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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When the TMR Manager detects a fault Lockstep state it is signaled to the
MicroBlaze processors by asserting a break signal, When Microblaze gets
a break vector from tmr Microblaze it's needed to clear/block the break
bit in the tmr manager before performing recovery.
In order to perform recovery need to perform the following steps.
1) Store all internal MicroBlaze registers in RAM
2) Execute a suspend instruction which asserts the reset signal
3) Restore all registers from RAM and execute an RTBD instruction to
return from the reset handler, to resume execution at the place
where the break occurred.
This API supports getting called from kernel space only.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Link: https://lore.kernel.org/r/20220627064024.771037-3-appana.durga.rao@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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Triple Modular Redundancy (TMR) Microblaze solution provides soft error
injection, detection, correction and recovery for Microblaze cores in the
system. The Xilinx/AMD Triple Modular Redundancy (TMR) solution in Vivado
provides all the necessary building blocks to implement a redundant
triplicated MicroBlaze subsystem. This processing subsystem is
fault-tolerant and continues to operate nominally after encountering an
error. Together with the capability to detect and recover from errors,
the implementation ensures the reliability of the entire subsystem.
When the break vector gets asserted because of error injection,
the break signal must be blocked before exiting from the break handler,
This commit adds support for xmb_manager_register api which updates the
TMR manager address and control register and error count and reset callback
function arguments, which will be used by the break handler to block the
break and call the error count callback function and reset callback
function.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Link: https://lore.kernel.org/r/20220627064024.771037-2-appana.durga.rao@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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Replace 'the the' with 'like the' in the comment.
Replace 'an' with 'a'.
Signed-off-by: Slark Xiao <slark_xiao@163.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220721071520.48384-1-slark_xiao@163.com
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There is a need to disable VM before jump to zero reset vector.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Asserhall <stefan.asserhall@xilinx.com>
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CONFIG_PREEMPTION is selected by CONFIG_PREEMPT and by CONFIG_PREEMPT_RT.
Both PREEMPT and PREEMPT_RT require the same functionality which today
depends on CONFIG_PREEMPT.
Switch the entry code over to use CONFIG_PREEMPTION.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20191015191821.11479-12-bigeasy@linutronix.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Since the enabling and disabling of IRQs within preempt_schedule_irq()
is contained in a need_resched() loop, we don't need the outer arch
code loop.
Signed-off-by: Valentin Schneider <valentin.schneider@arm.com>
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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The issue was that the service routine was sometimes
returning with the wrong flags set in the MSR.
In this case, EIP bit was set while returning to User Mode
which is an illegal combination since exceptions are always
handled in privileged mode.
In order for MicroBlaze to take an interrupt, the MSR must have IE=1,
BIP=0 and EIP=0.
Signed-off-by: Stefan Asserhall <stefana@xilinx.com>
Signed-off-by: Goran Bilski <goran@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Separate general purpose register restoring from MSR handling.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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This patch fixes two bugs in the Microblaze syscall trap handler when an invalid
syscall ID is used.
First, the range check on line 351 only checks for syscall IDs greater than
__NR_syscalls. A negative syscall ID (either passed to `syscall()` or as returned
by `do_syscall_trace_enter()` on error) will still satisfy this test and cause
the Linux kernel to access an invalid memory location and cause a kernel oops.
This has been fixed by also checking for r12 < 0.
Secondly, the current error recovery at line 378 returns using the wrong register
(r15 instead of r14) and does not restore the previous stack state. This has been
fixed by invoking `ret_from_trap` on error, setting r3 to `-ENOSYS`, similar to
what would happen when calling a valid syscall.
Signed-off-by: Jamie Garside <jamie.garside@york.ac.uk>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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No function change.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Better not to break block which do work together.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
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We need to keep building sigframes until no pending signals remain.
Wrap do_notify_resume() calls into loops; do _not_ allow syscall
restart logics to trigger after the first iteration.
Incidentally, comments about pending signals that should (somehow)
be in r18 are pure BS. Doesn't work that way and cannot work that
way, sorry...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
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solution a-la arm one - pick a callee-saved register (r30), set it
non-zero when entering a syscall, have sigreturn wrapper zero it out
and pass the value in it to do_notify_resume() as "in_syscall" (actually,
"restarts allowed") argument.
Note that we don't give a damn about ret_from_fork() - return value
is not restart-worthy anyway.
Possible remaining bug: on !MMU we still have _debug_exception()
restartable. If it hits with -ERESTART_... accidentally in r3, fun happens.
MMU does _not_ have _debug_exception() restartable. If that's decided to
be a bug (as I strongly suspect it to be), we'll just need to replace
setting r30 to 1 with setting r30 to 0 in !MMU _debug_exception().
Up to microblaze maintainers...
[folded a fix from Michal]
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
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Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
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Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Signed-off-by: Michal Simek <monstr@monstr.eu>
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Pull microblaze changes from Michal Simek.
* 'next' of git://git.monstr.eu/linux-2.6-microblaze:
microblaze: Setup correct pointer to TLS area
microblaze: Add TLS support to sys_clone
microblaze: ftrace: Pass the first calling instruction for dynamic ftrace
microblaze: Port OOM changes to do_page_fault
microblaze: Do not select GENERIC_GPIO by default
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Formerly unused Args 4/5 now load parent tid / child tid so the brid to
do_fork can pick up TLS from r10. Arg 3 still unused
There is also necessary to fix old glibc which do not setup r9/r10 (arg 4/5).
Simple clearing them is fine.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
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never used...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
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Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
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Just replace one dot with comma. New binutils can detect it.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Reset vector can be setup by bootloader and kernel doens't need
to touch it. If you require to setup reset vector, please use
CONFIG_MANUAL_RESET_VECTOR throught menuconfig.
It is not possible to setup address 0x0 as reset address because
make no sense to set it up at all.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: John Williams <john.williams@petalogix.com>
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If soft reset falls through with no hardware assisted reset, the best
we can do is jump to the reset vector and see what the bootloader left
for us.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: John Williams <john.williams@petalogix.com>
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Microblaze vector table stores several vectors (reset, user exception,
interrupt, debug exception and hardware exception).
All these functions can be below address 0x10000. If they are, wrong
vector table is genarated because jump is not setup from two instructions
(imm upper 16bit and brai lower 16bit).
Adding specific offset prevent problem if address is below 0x10000.
For this case only brai instruction is used.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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"la" pseudo instruction is only translation to "addik".
Use directly "addik" which is described in the MB reference guide.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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r0_ram pool was used for saving/restoring register
content if hw exception happen. This poll was replaced by
pt_pool_space with PT_SIZE size.
Based on this change SAVE_STATE_ARG_SPACE was removed which
caused that PTO offset is zero that's why is also removed.
r0_ram space was used as scratchpad by v850. In early
Microblaze Linux developing phase was this part of code
blindly copied.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Remove syscall counting space from r0_ram. Use special
syscall_debug_table pool for syscall statistic.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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This reverts commit 0e41c90908881a1b8205c66a66becec7d8d4eb4a.
Break jffs2 rootfs because the patch removes syscall calling
from kernel space.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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r16 and r17 should be saved across interrupt and exception handling.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Signal code uses r3 value which saved in restore_sigcontext to
rt_sigframe but it require to be zeroed. If is not zero rt_sigframe
contains wrong values.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Do not save return registers before rt_sigreturn is called.
_user_exception(syscall handler) already setup return address
that's why it is removed from rt_sigreturn_wrapper.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Kgdb uses brki r16, 0x18 instruction to call
low level _debug_exception function which save
current state to pt_regs and call microblaze_kgdb_break
function. _debug_exception should be called only from
the kernel space. User space calling is not supported
because user application debugging uses different handling.
pt_regs_to_gdb_regs loads additional special registers
which can't be changed
* Enable KGDB in Kconfig
* Remove ancient not-tested KGDB support
* Remove ancient _debug_exception code from entry.S
Only MMU KGDB support is supported.
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Jason Wessel <jason.wessel@windriver.com>
CC: John Williams <john.williams@petalogix.com>
CC: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
CC: linux-kernel@vger.kernel.org
Acked-by: Jason Wessel <jason.wessel@windriver.com>
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This is the first patch which add support for
user application debugging through brki rX, 0x18 vector.
This patch has side effect which also remove security issue
to use brki rX, 0x18 to freeze kernel.
Support for old gdb support via priviledged exception
(brk r0, r0) is still there. It will be remove in future.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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We need to save instruction and the latest Microblaze shouldn't
have any problem with it.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Syscall can be called only from userspace that's why
we don't need to check which space kernel come from.
Kernel syscall calling is not check and shouldn't come
throught this part of code.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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We can save one more instruction if PT_MODE is saved in delay slot
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Save instructions by using delay slot and
clear UMS only if kernel comes from user space.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Saving some instructions. Clear VMS bit if kernel comes
from kernel space.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Saving instructions by adding 2/3 addik instructions to one.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Saving instruction with delay slot usage.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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This change save one instruction if kernel comes from kernel
space.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Separate reg saving and mode setting.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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SAVE_STATE macro could be used by other rutines too.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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We are not working with values from MSR that's why
we can discard it and use r11 for different purpose without
saving/restoring.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Remove set_vms because UMS is cleared and VMS is already setup.
Optimize function calling which save one additional instruction.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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VMS is always setup because VM mode was before
exception/syscall/interrupt. Kernel continues in kernel mode
that's why we have to clear UMS bit if kernel comes from
user space.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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PT_MODE stores information if kernel comes from user
or kernel space. If come from user space, PT_MODE
contains 0. If come from kernel store, PT_MODE contains
non zero value. We don't need to save value 1. I am using
r1 register which contains non zero value.
This change save one additional instruction.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Appana Durga Kedareswara rao
Slark Xiao
Michal Simek
Thomas Gleixner
Valentin Schneider
Jamie Garside
Michal Simek
Al Viro
Linus Torvalds
Edgar E. Iglesias