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path: root/arch/mips/include/asm/mipsregs.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2016-06-15MIPS: Add define for Config.VI (virtual icache) bitJames Hogan1-0/+1
2016-06-15MIPS: Clean up RDHWR handlingJames Hogan1-1/+19
2016-05-28MIPS: Add 64-bit HTW fieldsJames Hogan1-0/+8
2016-05-28MIPS: Simplify DSP instruction encoding macrosJames Hogan1-90/+17
2016-05-28MIPS: Add missing tlbinvf/XPA microMIPS encodingsJames Hogan1-5/+7
2016-05-28MIPS: Add missing VZ accessor microMIPS encodingsJames Hogan1-9/+18
2016-05-28MIPS: Add inline asm encoding helpersJames Hogan1-0/+27
2016-05-28MIPS: Fix write_gc0_* macros when writing zeroJames Hogan1-2/+2
2016-05-28MIPS: Add definitions of SegCtl registers and use themMatt Redfearn1-0/+3
2016-05-17MIPS: Fix VZ probe gas errors with binutils <2.24James Hogan1-180/+293
2016-05-13MIPS: Add guest CP0 accessorsJames Hogan1-11/+330
2016-05-13MIPS: Add register definitions for VZ ASE registersJames Hogan1-0/+117
2016-05-13MIPS: Avoid magic numbers probing kscratch_maskJames Hogan1-1/+2
2016-05-13MIPS: Add defs & probing of [X]ContextConfigJames Hogan1-0/+6
2016-05-13MIPS: Add defs & probing of BadInstr[P] registersJames Hogan1-0/+3
2016-05-13MIPS: Add defs & probing of extended CP0_EBaseJames Hogan1-0/+3
2016-05-13MIPS: Define & use CP0_EBase bit definitionsJames Hogan1-1/+9
2016-05-13MIPS: Add & use CP0_EntryHi ASID definitionsJames Hogan1-0/+2
2016-05-13MIPS: Loongson-3: Fast TLB refill handlerHuacai Chen1-0/+6
2016-05-13MIPS: Loongson: Invalidate special TLBs when neededHuacai Chen1-0/+9
2016-05-13MIPS: Loongson: Add Loongson-3A R2 basic supportHuacai Chen1-0/+2
2016-05-13MIPS: Add and use watch register field definitionsJames Hogan1-0/+18
2016-05-13MIPS: Add and use CAUSEF_WP definitionJames Hogan1-0/+2
2016-05-13MIPS: Detect MIPSr6 Virtual Processor supportPaul Burton1-0/+1
2016-01-24MIPS: Update trap codesJames Hogan1-2/+10
2016-01-24MIPS: Move Cause.ExcCode trap codes to mipsregs.hJames Hogan1-0/+24
2016-01-24MIPS: Move definition of DC bit to mipsregs.hJames Hogan1-0/+2
2015-11-11MIPS: Tidy EntryLo bit definitions, add PFNPaul Burton1-9/+3
2015-11-11MIPS: CPS: Early debug using an ns16550-compatible UARTPaul Burton1-0/+3
2015-11-11MIPS: Fix duplicate CP0_* definitions.James Hogan1-0/+3
2015-09-22MIPS: cpu-features: Add cpu_has_ftlbJames Hogan1-0/+2
2015-09-03MIPS: Rearrange ENTRYLO field definitionsJames Hogan1-25/+27
2015-09-03MIPS: Treat CP1 control registers as unsigned ints.Ralf Baechle1-1/+1
2015-09-03MIPS: Use unsigned int when reading CP0 registersChris Packham1-2/+2
2015-08-26MIPS: Set up FTLB probability for I6400Markos Chandras1-0/+2
2015-06-21MIPS: R12000: Enable branch prediction global historyJoshua Kinard1-0/+13
2015-06-21MIPS: mipsregs.h: Add EntryLo bit definitionsJames Hogan1-0/+22
2015-04-08MIPS: math-emu: Define IEEE 754-2008 feature control bitsMaciej W. Rozycki1-2/+7
2015-04-08MIPS: math-emu: Implement the FCCR, FEXR and FENR registersMaciej W. Rozycki1-12/+57
2015-04-08MIPS: mipsregs.h: Reindent CP0 Cause macrosMaciej W. Rozycki1-16/+16
2015-04-08MIPS: mipsregs.h: Move TX39 macros out of the wayMaciej W. Rozycki1-33/+33
2015-04-08MIPS: mipsregs.h: Reorder CP1 macro definitionsMaciej W. Rozycki1-72/+75
2015-04-08MIPS: mipsregs.h: Remove broken commentsMaciej W. Rozycki1-6/+0
2015-03-31MIPS: Add architectural FDC IRQ fieldsJames Hogan1-0/+4
2015-03-31MIPS: Add arch CDMM definitions and probingJames Hogan1-0/+11
2015-02-21Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-0/+4
2015-02-20MIPS: Add set/clear CP0 macros for PageGrain registerSteven J. Hill1-0/+1
2015-02-17MIPS: asm: mipsregs: Add support for the LLADDR registerMarkos Chandras1-0/+2
2015-02-17MIPS: Add LLB bit and related feature for the Config 5 CP0 registerMarkos Chandras1-0/+1
2015-01-30MIPS: mipsregs.h: Add write_32bit_cp1_register()James Hogan1-0/+15
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