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2011-12-07MIPS: Netlogic: XLP CPU support.Jayachandran C5-8/+37
2011-12-07MIPS: Netlogic: Update default configJayachandran C1-8/+8
2011-12-07MIPS: Netlogic: Move code common with XLP to common/Jayachandran C19-441/+698
2011-12-07MIPS: Netlogic: No need to set -Werror in mips/xlrJayachandran C1-2/+0
2011-12-07MIPS: Netlogic: Use CPU_XLR instead of NLM_XLRJayachandran C4-7/+3
2011-12-07MIPS: Netlogic: Style fixes for PlatformJayachandran C1-5/+5
2011-12-07MIPS: Netlogic: Add basic MSI support for XLR/XLSGanesan Ramalingam4-1/+140
2011-12-07MIPS: Netlogic: Avoid unnecessary cache flushesJayachandran C1-3/+2
2011-12-07MIPS: Netlogic: add r4k_wait as the cpu_waitJayachandran C1-0/+1
2011-12-07MIPS: Netlogic: Change load addressJayachandran C1-1/+1
2011-12-07MIPS/Perf-events: Cleanup event->destroy at event initDeng-Cheng Zhu1-9/+6
2011-12-07MIPS/Perf-events: Remove pmu and event state checking in validate_event()Deng-Cheng Zhu1-15/+3
2011-12-07MIPS/Perf-events: Remove erroneous check on active_eventsDeng-Cheng Zhu1-5/+0
2011-12-07MIPS/Perf-events: Don't do validation on raw eventsDeng-Cheng Zhu1-32/+2
2011-12-07MIPS Kprobes: Support branch instructions probingManeesh Soni2-33/+117
2011-12-07MIPS Kprobes: Refactor branch emulationManeesh Soni3-45/+90
2011-12-07MIPS Kprobes: Deny probes on ll/sc instructionsManeesh Soni1-0/+31
2011-12-07MIPS Kprobes: Fix OOPS in arch_prepare_kprobe()Maneesh Soni1-3/+12
2011-12-07MIPS: irq: Remove IRQF_DISABLEDYong Zhang35-46/+40
2011-12-07MIPS: Handle initmem in systems with kernel not in add_memory_region() memDavid Daney4-14/+47
2011-12-07MIPS: Add fast get_user_pagesHillf Danton2-2/+317
2011-12-07MIPS: Hugetlb: Keep TLB cache hot while flushingHillf Danton1-1/+1
2011-12-07MIPS: GIO bus support for SGI IP22/28Thomas Bogendoerfer5-27/+490
2011-12-07MIPS: Octeon: Update DMA mapping operations for OCTEON II processors.David Daney2-3/+23
2011-12-07MIPS: Octeon: Update feature test functions for new chips and features.David Daney2-30/+126
2011-12-07MIPS: Octeon: Update SOC PCI related register definitions for new chips.David Daney7-83/+4909
2011-12-07MIPS: Octeon: Rearrange CVMX files in preperation for device treeDavid Daney11-24/+114
2011-12-07MIPS: Octeon: Update bootloader board type constants.David Daney3-3/+95
2011-12-07MIPS: Octeon: Move some Ethernet support files out of staging.David Daney52-5/+21643
2011-12-07MIPS: Oceton: Update model detection code for new chips.David Daney3-188/+1179
2011-12-07MIPS: Octeon: Update struct cvmx_bootinfo to v3.David Daney1-2/+8
2011-12-07MIPS: BMIPS: Add SMP support code for BMIPS43xx/BMIPS5000Kevin Cernekee4-0/+717
2011-12-07MIPS: Add board_ebase_setup()Kevin Cernekee2-0/+4
2011-12-07MIPS: Add NMI notifierKevin Cernekee2-0/+21
2011-12-07MIPS: BMIPS: Introduce bmips.hKevin Cernekee1-0/+110
2011-12-07MIPS: BMIPS: Add set/clear CP0 macros for BMIPS operationsKevin Cernekee1-1/+8
2011-12-07MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPSKevin Cernekee3-2/+6
2011-12-07MIPS: Clean up whitespace warning in hazards.hKevin Cernekee1-2/+2
2011-12-07MIPS: BMIPS: Fix up Kconfig settingsKevin Cernekee1-20/+14
2011-12-07MIPS: BCM63XX: generate WLAN MAC address after registering ethernet devices.Florian Fainelli1-12/+13
2011-12-07MIPS: BCM63xx: Fix GPIO set/get for BCM6345Florian Fainelli2-5/+37
2011-12-07MIPS: BCM63xx: Remove BCM6345 hacks to read base boot addressFlorian Fainelli2-16/+7
2011-12-07MIPS: BCM63xx: Fix SDRAM size computation for BCM6345Florian Fainelli2-2/+6
2011-12-07MIPS: BCM63XX: Add support for bcm6368 CPU.Maxime Bizon11-27/+377
2011-12-07MIPS: BCM63XX: Add external irq support for non 6348 CPUs.Maxime Bizon3-43/+149
2011-12-07MIPS: BCM63XX: Handle 64 bits irq stat register in irq code.Maxime Bizon1-6/+76
2011-12-07MIPS: BCM63XX: Introduce bcm_readq & bcm_writeq.Maxime Bizon1-0/+2
2011-12-07MIPS: BCM63XX: Prepare irq code to handle different external irq hardware implementation.Maxime Bizon3-44/+79
2011-12-07MIPS: BCM63XX: Change irq code to prepare for per-cpu peculiarity.Maxime Bizon2-11/+85
2011-12-07MIPS: BCM63XX: Add more register sets & missing register definitions.Maxime Bizon2-2/+261