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2019-12-20riscv: move sifive_l2_cache.c to drivers/socChristoph Hellwig1-1/+0
2019-11-28Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremapLinus Torvalds1-1/+1
2019-11-17riscv: add nommu supportChristoph Hellwig1-2/+1
2019-11-11riscv: use the generic ioremap codeChristoph Hellwig1-1/+0
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig1-0/+3
2019-07-03riscv: Introduce huge page support for 32/64bit kernelAlexandre Ghiti1-0/+2
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-05-16RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCsYash Shah1-0/+1
2019-05-16riscv: move switch_mm to its own fileGary Guo1-0/+1
2019-03-26RISC-V: Always compile mm/init.c with cmodel=medany and notraceAnup Patel1-0/+6
2017-11-30RISC-V: Flush I$ when making a dirty page executableAndrew Waterman1-0/+1
2017-09-26RISC-V: Build InfrastructurePalmer Dabbelt1-0/+4