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2021-02-12Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linuxLinus Torvalds2-6/+3
Pull arm64 fix from Catalin Marinas: "Fix PTRACE_PEEKMTETAGS access to an mmapped region before the first write" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: mte: Allow PTRACE_PEEKMTETAGS access to the zero page
2021-02-12arm64: mte: Allow PTRACE_PEEKMTETAGS access to the zero pageCatalin Marinas2-6/+3
The ptrace(PTRACE_PEEKMTETAGS) implementation checks whether the user page has valid tags (mapped with PROT_MTE) by testing the PG_mte_tagged page flag. If this bit is cleared, ptrace(PTRACE_PEEKMTETAGS) returns -EIO. A newly created (PROT_MTE) mapping points to the zero page which had its tags zeroed during cpu_enable_mte(). If there were no prior writes to this mapping, ptrace(PTRACE_PEEKMTETAGS) fails with -EIO since the zero page does not have the PG_mte_tagged flag set. Set PG_mte_tagged on the zero page when its tags are cleared during boot. In addition, to avoid ptrace(PTRACE_PEEKMTETAGS) succeeding on !PROT_MTE mappings pointing to the zero page, change the __access_remote_tags() check to (vm_flags & VM_MTE) instead of PG_mte_tagged. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Fixes: 34bfeea4a9e9 ("arm64: mte: Clear the tags when a page is mapped in user-space with PROT_MTE") Cc: <stable@vger.kernel.org> # 5.10.x Cc: Will Deacon <will@kernel.org> Reported-by: Luis Machado <luis.machado@linaro.org> Tested-by: Luis Machado <luis.machado@linaro.org> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Link: https://lore.kernel.org/r/20210210180316.23654-1-catalin.marinas@arm.com
2021-02-12Merge branch 'x86/cleanups' into x86/mmIngo Molnar15-111/+60
Merge recent cleanups to the x86 MM code to resolve a conflict. Conflicts: arch/x86/mm/fault.c Signed-off-by: Ingo Molnar <mingo@kernel.org>
2021-02-11Merge tag 'powerpc-5.11-8' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linuxLinus Torvalds3-9/+12
Pull powerpc fix from Michael Ellerman: "One fix for a regression seen in io_uring, introduced by our support for KUAP (Kernel User Access Prevention) with the Hash MMU. Thanks to Aneesh Kumar K.V, and Zorro Lang" * tag 'powerpc-5.11-8' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/kuap: Allow kernel thread to access userspace after kthread_use_mm
2021-02-11dts: marvell: add CM3 SRAM memory to cp11x ethernet device treeKonstantin Porotchkin1-1/+1
CM3 SRAM address space will be used for Flow Control configuration. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11bpf: Add per-program recursion prevention mechanismAlexei Starovoitov1-0/+15
Since both sleepable and non-sleepable programs execute under migrate_disable add recursion prevention mechanism to both types of programs when they're executed via bpf trampoline. Signed-off-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20210210033634.62081-5-alexei.starovoitov@gmail.com
2021-02-11bpf: Compute program stats for sleepable programsAlexei Starovoitov1-19/+12
Since sleepable programs don't migrate from the cpu the excution stats can be computed for them as well. Reuse the same infrastructure for both sleepable and non-sleepable programs. run_cnt -> the number of times the program was executed. run_time_ns -> the program execution time in nanoseconds including the off-cpu time when the program was sleeping. Signed-off-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: Andrii Nakryiko <andrii@kernel.org> Acked-by: KP Singh <kpsingh@kernel.org> Link: https://lore.kernel.org/bpf/20210210033634.62081-4-alexei.starovoitov@gmail.com
2021-02-11Merge tag 'samsung-soc-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/socArnd Bergmann2-9/+8
Samsung mach/soc changes for v5.12 Three fixes for S3C24xx: one for building with clang and two for warnings. * tag 'samsung-soc-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: s3c: irq-s3c24xx: staticize local functions ARM: s3c: irq-s3c24xx: include headers for missing declarations ARM: s3c: fix fiq for clang IAS Link: https://lore.kernel.org/r/20210211082254.7934-1-krzk@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-11Merge tag 'zynq-dt-for-v5.12-v2' of https://github.com/Xilinx/linux-xlnx into arm/dtArnd Bergmann2-0/+133
ARM: dts: Zynq DT changes for v5.12-v2 - Add Ebang board support - Add missing zturn boards in dt binding - And convert Zynq QSPI binding * tag 'zynq-dt-for-v5.12-v2' of https://github.com/Xilinx/linux-xlnx: dt-bindings: spi: zynq: Convert Zynq QSPI binding to yaml dt-bindings: arm: xilinx: Add missing Zturn boards ARM: dts: ebaz4205: add pinctrl entries for switches ARM: dts: add Ebang EBAZ4205 device tree dt-bindings: arm: add Ebang EBAZ4205 board dt-bindings: add ebang vendor prefix Link: https://lore.kernel.org/r/19e0e0c9-1bed-bba5-6c80-6903937b3d96@xilinx.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-11Merge branch 'dt-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti into arm/dtArnd Bergmann2-0/+15
* 'dt-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti: arm: dts: visconti: Add DT support for Toshiba Visconti5 GPIO driver Link: https://lore.kernel.org/r/20210210173210.nnytfyrkkj6ylrtb@toshiba.co.jp Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-11Merge tag 'aspeed-5.12-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/dtArnd Bergmann13-7/+1534
ASPEED device tree updates for 5.12 - New machines * Ampere Mt. Jade, an AST2500 BMC for an x86 server * IBM Everest, an AST2600 BMC for a Power10 server * Supermicro x11spi, an AST2500 BMC for an ARM server - AST2600 eMMC clock phase configuration - Proper clock support for LPC snoop - Misc updates to ethanolx, mowgli, ast2600evb, g220a, and rainier * tag 'aspeed-5.12-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: ARM: dts: aspeed: ast2600evb: Add enable ehci and uhci ARM: dts: aspeed: mowgli: Add i2c rtc device ARM: dts: aspeed: amd-ethanolx: Enable secondary LPC snooping address ARM: dts: aspeed: Add Everest BMC machine ARM: dts: aspeed: inspur-fp5280g2: Add ipsps1 driver ARM: dts: aspeed: inspur-fp5280g2: Add GPIO line names ARM: dts: aspeed: Add Supermicro x11spi BMC machine ARM: dts: aspeed: g220a: Fix some gpio ARM: dts: aspeed: g220a: Enable ipmb ARM: dts: aspeed: rainier: Add eMMC clock phase compensation ARM: dts: aspeed: Add LCLK to lpc-snoop ARM: dts: aspeed: Add device tree for Ampere's Mt. Jade BMC Link: https://lore.kernel.org/r/CACPK8XfQgGch5bK3YD0La+CE2L5DxVa1MNw6m1fc40j0w7e9Tw@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-11arm/xen: Don't probe xenbus as part of an early initcallJulien Grall1-2/+0
After Commit 3499ba8198cad ("xen: Fix event channel callback via INTX/GSI"), xenbus_probe() will be called too early on Arm. This will recent to a guest hang during boot. If the hang wasn't there, we would have ended up to call xenbus_probe() twice (the second time is in xenbus_probe_initcall()). We don't need to initialize xenbus_probe() early for Arm guest. Therefore, the call in xen_guest_init() is now removed. After this change, there is no more external caller for xenbus_probe(). So the function is turned to a static one. Interestingly there were two prototypes for it. Cc: stable@vger.kernel.org Fixes: 3499ba8198cad ("xen: Fix event channel callback via INTX/GSI") Reported-by: Ian Jackson <iwj@xenproject.org> Signed-off-by: Julien Grall <jgrall@amazon.com> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Link: https://lore.kernel.org/r/20210210170654.5377-1-julien@xen.org Signed-off-by: Juergen Gross <jgross@suse.com>
2021-02-10Revert "dts: phy: add GPIO number and active state used for phy reset"Palmer Dabbelt1-1/+0
VSC8541 phys need a special reset sequence, which the driver doesn't currentlny support. As a result enabling the reset via GPIO essentially guarnteees that the device won't work correctly. We've been relying on bootloaders to reset the device for years, with this revert we'll go back to doing so until we can sort out how to get the reset sequence into the kernel. This reverts commit a0fa9d727043da2238432471e85de0bdb8a8df65. Fixes: a0fa9d727043 ("dts: phy: add GPIO number and active state used for phy reset") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-02-10Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netDavid S. Miller85-385/+435
2021-02-10x86/pci: Create PCI/MSI irqdomain after x86_init.pci.arch_init()Thomas Gleixner1-4/+11
Invoking x86_init.irqs.create_pci_msi_domain() before x86_init.pci.arch_init() breaks XEN PV. The XEN_PV specific pci.arch_init() function overrides the default create_pci_msi_domain() which is obviously too late. As a consequence the XEN PV PCI/MSI allocation goes through the native path which runs out of vectors and causes malfunction. Invoke it after x86_init.pci.arch_init(). Fixes: 6b15ffa07dc3 ("x86/irq: Initialize PCI/MSI domain at PCI init time") Reported-by: Juergen Gross <jgross@suse.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/87pn18djte.fsf@nanos.tec.linutronix.de
2021-02-10x86/{fault,efi}: Fix and rename efi_recover_from_page_fault()Andy Lutomirski3-10/+19
efi_recover_from_page_fault() doesn't recover -- it does a special EFI mini-oops. Rename it to make it clear that it crashes. While renaming it, I noticed a blatant bug: a page fault oops in a different thread happening concurrently with an EFI runtime service call would be misinterpreted as an EFI page fault. Fix that. This isn't quite exact. The situation could be improved by using a special CS for calls into EFI. [ bp: Massage commit message and simplify in interrupt check. ] Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/f43b1e80830dc78ed60ed8b0826f4f189254570c.1612924255.git.luto@kernel.org
2021-02-11arm: dts: visconti: Add DT support for Toshiba Visconti5 GPIO driverNobuhiro Iwamatsu2-0/+15
Add the GPIO node in Toshiba Visconti5 SoC-specific DT file. And enable the GPIO node in TMPV7708 RM main board's board-specific DT file. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Reviewed-by: Punit Agrawal <punit1.agrawal@toshiba.co.jp> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2021-02-10x86/fault: Don't run fixups for SMAP violationsAndy Lutomirski1-3/+6
A SMAP-violating kernel access is not a recoverable condition. Imagine kernel code that, outside of a uaccess region, dereferences a pointer to the user range by accident. If SMAP is on, this will reliably generate as an intentional user access. This makes it easy for bugs to be overlooked if code is inadequately tested both with and without SMAP. This was discovered because BPF can generate invalid accesses to user memory, but those warnings only got printed if SMAP was off. Make it so that this type of error will be discovered with SMAP on as well. [ bp: Massage commit message. ] Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/66a02343624b1ff46f02a838c497fc05c1a871b3.1612924255.git.luto@kernel.org
2021-02-10x86/fault: Don't look for extable entries for SMEP violationsAndy Lutomirski1-2/+2
If the kernel gets a SMEP violation or a fault that would have been a SMEP violation if it had SMEP support, it shouldn't run fixups. Just OOPS. [ bp: Massage commit message. ] Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/46160d8babce2abf1d6daa052146002efa24ac56.1612924255.git.luto@kernel.org
2021-02-10perf/x86/rapl: Fix psys-energy event on Intel SPR platformZhang Rui1-12/+9
There are several things special for the RAPL Psys energy counter, on Intel Sapphire Rapids platform. 1. it contains one Psys master package, and only CPUs on the master package can read valid value of the Psys energy counter, reading the MSR on CPUs in the slave package returns 0. 2. The master package does not have to be Physical package 0. And when all the CPUs on the Psys master package are offlined, we lose the Psys energy counter, at runtime. 3. The Psys energy counter can be disabled by BIOS, while all the other energy counters are not affected. It is not easy to handle all of these in the current RAPL PMU design because a) perf_msr_probe() validates the MSR on some random CPU, which may either be in the Psys master package or in the Psys slave package. b) all the RAPL events share the same PMU, and there is not API to remove the psys-energy event cleanly, without affecting the other events in the same PMU. This patch addresses the problems in a simple way. First, by setting .no_check bit for RAPL Psys MSR, the psys-energy event is always added, so we don't have to check the Psys ENERGY_STATUS MSR on master package. Then, by removing rapl_not_visible(), the psys-energy event is always available in sysfs. This does not affect the previous code because, for the RAPL MSRs with .no_check cleared, the .is_visible() callback is always overriden in the perf_msr_probe() function. Note, although RAPL PMU is die-based, and the Psys energy counter MSR on Intel SPR is package scope, this is not a problem because there is only one die in each package on SPR. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/20210204161816.12649-3-rui.zhang@intel.com
2021-02-10perf/x86/rapl: Only check lower 32bits for RAPL energy countersZhang Rui1-5/+8
In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the energy counter. On previous platforms, the higher 32bits are reverved and always return Zero. But on Intel SapphireRapids platform, the higher 32bits are reused for other purpose and return non-zero value. Thus check the lower 32bits only for these ENERGY_COUTNER MSRs, to make sure the RAPL PMU events are not added erroneously when higher 32bits contain non-zero value. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/20210204161816.12649-2-rui.zhang@intel.com
2021-02-10perf/x86/rapl: Add msr mask supportZhang Rui2-4/+10
In some cases, when probing a perf MSR, we're probing certain bits of the MSR instead of the whole register, thus only these bits should be checked. For example, for RAPL ENERGY_STATUS MSR, only the lower 32 bits represents the energy counter, and the higher 32bits are reserved. Introduce a new mask field in struct perf_msr to allow probing certain bits of a MSR. This change is transparent to the current perf_msr_probe() users. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/20210204161816.12649-1-rui.zhang@intel.com
2021-02-10perf/x86/kvm: Add Cascade Lake Xeon steppings to isolation_ucodes[]Jim Mattson1-0/+3
Cascade Lake Xeon parts have the same model number as Skylake Xeon parts, so they are tagged with the intel_pebs_isolation quirk. However, as with Skylake Xeon H0 stepping parts, the PEBS isolation issue is fixed in all microcode versions. Add the Cascade Lake Xeon steppings (5, 6, and 7) to the isolation_ucodes[] table so that these parts benefit from Andi's optimization in commit 9b545c04abd4f ("perf/x86/kvm: Avoid unnecessary work in guest filtering"). Signed-off-by: Jim Mattson <jmattson@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/20210205191324.2889006-1-jmattson@google.com
2021-02-10x86/fault: Rename no_context() to kernelmode_fixup_or_oops()Andy Lutomirski1-18/+10
The name no_context() has never been very clear. It's only called for faults from kernel mode, so rename it and change the no-longer-useful user_mode(regs) check to a WARN_ON_ONCE. Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/c21940efe676024bb4bc721f7d70c29c420e127e.1612924255.git.luto@kernel.org
2021-02-10x86/fault: Bypass no_context() for implicit kernel faults from usermodeAndy Lutomirski1-27/+32
Drop an indentation level and remove the last user_mode(regs) == true caller of no_context() by directly OOPSing for implicit kernel faults from usermode. Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/6e3d1129494a8de1e59d28012286e3a292a2296e.1612924255.git.luto@kernel.org
2021-02-10x86/fault: Split the OOPS code out from no_context()Andy Lutomirski1-54/+62
Not all callers of no_context() want to run exception fixups. Separate the OOPS code out from the fixup code in no_context(). Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/450f8d8eabafb83a5df349108c8e5ea83a2f939d.1612924255.git.luto@kernel.org
2021-02-10x86/fault: Improve kernel-executing-user-memory handlingAndy Lutomirski1-3/+18
Right now, the case of the kernel trying to execute from user memory is treated more or less just like the kernel getting a page fault on a user access. In the failure path, it checks for erratum #93, tries to otherwise fix up the error, and then oopses. If it manages to jump to the user address space, with or without SMEP, it should not try to resolve the page fault. This is an error, pure and simple. Rearrange the code so that this case is caught early, check for erratum #93, and bail out. [ bp: Massage commit message. ] Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/ab8719c7afb8bd501c4eee0e36493150fbbe5f6a.1612924255.git.luto@kernel.org
2021-02-10x86/fault: Correct a few user vs kernel checks wrt WRUSSAndy Lutomirski1-4/+11
In general, page fault errors for WRUSS should be just like get_user(), etc. Fix three bugs in this area: There is a comment that says that, if the kernel can't handle a page fault on a user address due to OOM, the OOM-kill-and-retry logic would be skipped. The code checked kernel *privilege*, not kernel mode, so it missed WRUSS. This means that the kernel would malfunction if it got OOM on a WRUSS fault -- this would be a kernel-mode, user-privilege fault, and the OOM killer would be invoked and the handler would retry the faulting instruction. A failed user access from kernel while a fatal signal is pending should fail even if the instruction in question was WRUSS. do_sigbus() should not send SIGBUS for WRUSS -- it should handle it like any other kernel mode failure. Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/a7b7bcea730bd4069e6b7e629236bb2cf526c2fb.1612924255.git.luto@kernel.org
2021-02-10x86/fault: Document the locking in the fault_signal_pending() pathAndy Lutomirski1-1/+4
If fault_signal_pending() returns true, then the core mm has unlocked the mm for us. Add a comment to help future readers of this code. Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/c56de3d103f40e6304437b150aa7b215530d23f7.1612924255.git.luto@kernel.org
2021-02-10x86/fault/32: Move is_f00f_bug() to do_kern_addr_fault()Andy Lutomirski1-5/+7
bad_area() and its relatives are called from many places in fault.c, and exactly one of them wants the F00F workaround. __bad_area_nosemaphore() no longer contains any kernel fault code, which prepares for further cleanups. Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/e9668729a48ce6754022b0a4415631e8ebdd00e7.1612924255.git.luto@kernel.org
2021-02-10x86/fault: Fold mm_fault_error() into do_user_addr_fault()Andy Lutomirski1-52/+45
mm_fault_error() is logically just the end of do_user_addr_fault(). Combine the functions. This makes the code easier to read. Most of the churn here is from renaming hw_error_code to error_code in do_user_addr_fault(). This makes no difference at all to the generated code (objdump -dr) as compared to changing noinline to __always_inline in the definition of mm_fault_error(). Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/dedc4d9c9b047e51ce38b991bd23971a28af4e7b.1612924255.git.luto@kernel.org
2021-02-10x86/fault: Skip the AMD erratum #91 workaround on unaffected CPUsAndy Lutomirski1-0/+13
According to the Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors, only early revisions of family 0xF are affected. This will avoid unnecessarily fetching instruction bytes before sending SIGSEGV to user programs. Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/477173b7784bc28afb3e53d76ae5ef143917e8dd.1612924255.git.luto@kernel.org
2021-02-10x86/fault: Fix AMD erratum #91 errata fixup for user codeAndy Lutomirski1-10/+17
The recent rework of probe_kernel_address() and its conversion to get_kernel_nofault() inadvertently broke is_prefetch(). Before this change, probe_kernel_address() was used as a sloppy "read user or kernel memory" helper, but it doesn't do that any more. The new get_kernel_nofault() reads *kernel* memory only, which completely broke is_prefetch() for user access. Adjust the code to the correct accessor based on access mode. The manual address bounds check is no longer necessary, since the accessor helpers (get_user() / get_kernel_nofault()) do the right thing all by themselves. As a bonus, by using the correct accessor, the open-coded address bounds check is not needed anymore. [ bp: Massage commit message. ] Fixes: eab0c6089b68 ("maccess: unify the probe kernel arch hooks") Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Christoph Hellwig <hch@lst.de> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/b91f7f92f3367d2d3a88eec3b09c6aab1b2dc8ef.1612924255.git.luto@kernel.org
2021-02-10x86/pv: Rework arch_local_irq_restore() to not use popfJuergen Gross10-93/+8
POPF is a rather expensive operation, so don't use it for restoring irq flags. Instead, test whether interrupts are enabled in the flags parameter and enable interrupts via STI in that case. This results in the restore_fl paravirt op to be no longer needed. Suggested-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210120135555.32594-7-jgross@suse.com
2021-02-10x86/xen: Drop USERGS_SYSRET64 paravirt callJuergen Gross10-61/+8
USERGS_SYSRET64 is used to return from a syscall via SYSRET, but a Xen PV guest will nevertheless use the IRET hypercall, as there is no sysret PV hypercall defined. So instead of testing all the prerequisites for doing a sysret and then mangling the stack for Xen PV again for doing an iret just use the iret exit from the beginning. This can easily be done via an ALTERNATIVE like it is done for the sysenter compat case already. It should be noted that this drops the optimization in Xen for not restoring a few registers when returning to user mode, but it seems as if the saved instructions in the kernel more than compensate for this drop (a kernel build in a Xen PV guest was slightly faster with this patch applied). While at it remove the stale sysret32 remnants. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210120135555.32594-6-jgross@suse.com
2021-02-10x86/pv: Switch SWAPGS to ALTERNATIVEJuergen Gross8-47/+13
SWAPGS is used only for interrupts coming from user mode or for returning to user mode. So there is no reason to use the PARAVIRT framework, as it can easily be replaced by an ALTERNATIVE depending on X86_FEATURE_XENPV. There are several instances using the PV-aware SWAPGS macro in paths which are never executed in a Xen PV guest. Replace those with the plain swapgs instruction. For SWAPGS_UNSAFE_STACK the same applies. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Andy Lutomirski <luto@kernel.org> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20210120135555.32594-5-jgross@suse.com
2021-02-10x86/xen: Use specific Xen pv interrupt entry for DFJuergen Gross3-3/+12
Xen PV guests don't use IST. For double fault interrupts, switch to the same model as NMI. Correct a typo in a comment while copying it. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20210120135555.32594-4-jgross@suse.com
2021-02-10x86/xen: Use specific Xen pv interrupt entry for MCEJuergen Gross3-2/+19
Xen PV guests don't use IST. For machine check interrupts, switch to the same model as debug interrupts. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20210120135555.32594-3-jgross@suse.com
2021-02-10ARM: dts: aspeed: ast2600evb: Add enable ehci and uhciRyan Chen1-0/+8
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Link: https://lore.kernel.org/r/20201009024937.11246-4-ryan_chen@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-10ARM: dts: aspeed: mowgli: Add i2c rtc deviceBen Pai1-0/+5
This system uses a rx8900 compatible rtc device. Signed-off-by: Ben Pai <Ben_Pai@wistron.com> Link: https://lore.kernel.org/r/20210121073146.28217-1-Ben_Pai@wistron.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-10ARM: dts: aspeed: amd-ethanolx: Enable secondary LPC snooping addressKonstantin Aladyshev1-1/+1
AMD EthanolX CRB uses 2-byte POST codes which are sent to ports 0x80/0x81. Currently ASPEED controller snoops only 0x80 port and therefore captures only the lower byte of each POST code. Enable secondary LPC snooping address to capture the higher byte of POST codes. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210127182326.424-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-10ARM: dts: ebaz4205: add pinctrl entries for switchesMichael Walle1-0/+23
Add the pinctrl entries for the GPIOs which are connected to the push buttons on this board. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20210201133000.23402-1-michael@walle.cc Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-10ARM: dts: add Ebang EBAZ4205 device treeMichael Walle2-0/+110
The Ebang EBAZ4205 is a simple board based on the Xilinx Zynq-7000 SoC. Its features are: - one serial port - 256 MB RAM - 128 MB NAND flash - SDcard slot - IP101GA 10/100 Mbit Ethernet PHY (connected to PL IOs) - two LEDs (connected to PL IOs) - one Push Button (connect to PL IOs) - (optional) RTC - (optional) Input voltage supervisor The NAND flash is not supported in mainline linux yet. Unfortunately, the PHY is connected via the PL, thus for working ethernet the FPGA has to be configured. Also, depending on the board variant, the PHY has no external crystal and its clock needs to be driven by the PL. FCLK3 is used for this and is kept enabled. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20210120194033.26970-4-michael@walle.cc Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-10Merge tag 'zynqmp-soc-for-v5.12' of https://github.com/Xilinx/linux-xlnx into arm/defconfigArnd Bergmann1-0/+1
arm64: soc: ZynqMP SoC changes for v5.12 - Enable clock driver for ZynqMP in defconfig * tag 'zynqmp-soc-for-v5.12' of https://github.com/Xilinx/linux-xlnx: arm64: defconfig: enable clock driver for ZynqMP platforms Link: https://lore.kernel.org/r/2b0f6314-13ba-375a-9231-925b0a07be82@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-10Merge tag 'imx-soc-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/socArnd Bergmann2-25/+4
i.MX SoC update for 5.12: - Drop unused IMX_GPIO_NR() macro. - Remove KSZ8081 PHY fixup from i.MX6UL machine code, because it only applies for KSZ8081RNA with 50MHz clock source, but breaks other KSZ8081 PHY configurations. - Add a print of CPU type and SOC revision for i.MX6UL during boot. * tag 'imx-soc-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: Remove unused IMX_GPIO_NR() macro ARM: mach-imx: imx6ul: Print SOC revision on boot ARM: imx: mach-imx6ul: remove 14x14 EVK specific PHY fixup Link: https://lore.kernel.org/r/20210204120150.26186-2-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09Merge tag 'socfpga_dts_fix_for_v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/fixesArnd Bergmann1-2/+2
SoCFPGA Agilex fix for v5.12 - Fix PHY interface register offset for GMACs * tag 'socfpga_dts_fix_for_v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: agilex: fix phy interface bit shift for gmac1 and gmac2 Link: https://lore.kernel.org/r/20210208203703.36109-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09Merge tag 'v5.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dtArnd Bergmann15-246/+685
New boards: Radxa Rock Pi E, NanoPi M4B More fixed indices for mmc nodes; removal of obsolete amba bus nodes; nand-flash-controller nodes for px30 and rk3308; rk3399 pcie ranges fix; board-level fixes for Helios64, NanoPi and Rock960; more sound support for rock64 and rockpro64 and cleanups to make dt-bindings happier. * tag 'v5.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (24 commits) arm64: dts: rockchip: more user friendly name of sound nodes arm64: dts: rockchip: rename pinctrl nodename to gmac2io for nanopi-r2s board arm64: dts: rockchip: assign a fixed index to mmc devices on rk3368 boards arm64: dts: rockchip: assign a fixed index to mmc devices on rk3308 boards arm64: dts: rockchip: assign a fixed index to mmc devices on px30 boards arm64: dts: rockchip: cleanup cpu_thermal node of rk3399-rock960.dts arm64: dts: rockchip: Remove bogus "amba" bus nodes arm64: dts: rockchip: Light "sys" LED on NanoPi R2S arm64: dts: rockchip: fix ranges property format for rk3399 pcie node arm64: dts: rockchip: Rely on SoC external pull up on pmic-int-l on Helios64 arm64: dts: rockchip: Add NanoPi M4B board arm64: dts: rockchip: Move ep-gpios property to nanopc-t4 from nanopi4 arm64: dts: rockchip: Add NFC node for PX30 SoC arm64: dts: rockchip: Add NFC node for RK3308 SoC arm64: dts: rockchip: rk3328: Add Radxa ROCK Pi E dt-bindings: arm: rockchip: Add Radxa ROCK Pi E arm64: dts: rockchip: rk3328: Add clock_in_out property to gmac2phy node arm64: dts: rockchip: rename thermal subnodes for rk3399 arm64: dts: rockchip: rename thermal subnodes for rk3368 arm64: dts: rockchip: add SPDIF node for rk3399-rockpro64 ... Link: https://lore.kernel.org/r/12699743.uLZWGnKmhe@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09Merge tag 'v5.12-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dtArnd Bergmann6-150/+205
Fixed indices for mmc nodes; removal of obsolete amba bus nodes; addition of nand flash controller odes to rk3036, rk2928, rv1108; gpu node for rk3288-miqi and some cleanups to make dtbscheck happier. * tag 'v5.12-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: assign a fixed index to mmc devices on rv1108 boards ARM: dts: rockchip: assign a fixed index to mmc devices on rk322x boards ARM: dts: rockchip: Remove bogus "amba" bus nodes ARM: dts: rockchip: Add NFC node for RK3036 SoC ARM: dts: rockchip: Add NFC node for RK2928 and other SoCs ARM: dts: rockchip: Add NFC node for RV1108 SoC ARM: dts: rockchip: rename thermal subnodes for rk3288 ARM: dts: rockchip: add QoS register compatibles for rk3288 ARM: dts: rockchip: add QoS register compatibles for rk3066/rk3188 ARM: dts: rockchip: add gpu node to rk3288-miqi Link: https://lore.kernel.org/r/2184150.ElGaqSPkdT@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09Merge tag 'actions-arm-dt-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-actions into arm/dtArnd Bergmann6-33/+232
Actions Semi ARM DT changes for v5.12: Updates to the existing S500 ARM SoC. Support has been added for CMU (Clock Management Unit), Reset controller, DMA, Pinctrl/GPIO, MMC, I2C and SIRQ (interrupt controller). Since the CMU support is added, the dummy fixed clock used for the UART controller has been removed for all S500 based boards and proper UART clock from CMU is used. Added uSD support and I2C pinctrl configuration for Roseapplepi board based on S500 SoC. This will make the board boot mainline with a distro from uSD card. The I2C pinctrl config is added specifically for the PMIC which is currently under review. * tag 'actions-arm-dt-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-actions: arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration arm: dts: owl-s500-roseapplepi: Add uSD support arm: dts: owl-s500: Add SIRQ controller arm: dts: owl-s500: Add I2C support arm: dts: owl-s500: Add MMC support arm: dts: owl-s500: Add pinctrl & GPIO support arm: dts: owl-s500: Add DMA controller arm: dts: owl-s500: Add Reset controller arm: dts: owl-s500: Set CMU clocks for UARTs arm: dts: owl-s500: Add Clock Management Unit Link: https://lore.kernel.org/r/20210205050346.GA7619@thinkpad Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09Merge tag 'imx-dt64-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dtArnd Bergmann54-274/+4542
i.MX arm64 device tree update for 5.12: - New board support: Beacon i.MX8M Nano development kit, i.MX8MM Nitrogen, Gateworks i.MX 8M Mini Development Kits, phyBOARD-Pollux-i.MX8MP, Librem5 Evergreen. - Update imx8mm-beacon to drop unused clock-names reference, and add more pinctrl states for USDHC1. - Support soc unique ID read with NVMEM on i.MX8M SoCs. - A series from Biwen Li to add interrupt line for RTC device on Layerscape SoCs. - A couple of patch sets to update imx8mq-librem5 support around regulators, RTC, charger, display, etc. - A series from Joakim Zhang to improve i.MX8M FEC device configuration. - A series from Kuldeep Singh to enable flexcan support for LX2160A and LS1028A. - A series from Lucas Stach to update ZII devices around audio, USB, I2C pin configuration and UCS1002 ALERT. - A series from Michael Walle to update Layerscape device trees to use constants in the clockgen phandle, add sl28 variant 1 and enable SATA. - A few patches from Russell King to improve support for a couple of LX2160A boards. - A series from Shengjiu Wang to add more audio support for imx8mn-evk. - Other small and random updates. * tag 'imx-dt64-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (71 commits) arm64: dts: imx: Add i.mx8mm nitrogen basic dts support arm64: dts: zii-rmb3: enable RMI4 reduced reporting arm64: dts: zii-ultra: only trigger IRQ on falling edge ucs1002 ALERT pin arm64: dts: zii-ultra: limit USB ports to USB2 speed arm64: dts: zii-ultra: fix i2c pin configuration arm64: dts: zii-ultra: add sound support arm64: dts: ls1028a: Enable flexcan support for LS1028A-RDB/QDS arm64: dts: ls1028a: Update flexcan properties arm64: dts: lx2160a: Add flexcan support arm64: dts: fsl-ls1012a-frdm: add spi-uart device arm64: dts: fsl-ls1012a-rdb: add i2c devices arm64: dts: imx8mn-beacon-som: Enable QSPI on SOM arm64: dts: imx8mn: Add fspi node arm64: dts: Add Librem5 Evergreen arm64: dts: imx8mq-librem5: set regulators boot-on arm64: dts: imx8mq-librem5: enable the LCD panel arm64: dts: imx8mq-librem5: Add LCD_1V8 regulator arm64: dts: imx8mq-librem5: Add usb-c chip as supplier for the charger arm64: dts: imx8mq-librem5: Don't mark buck3 as always on arm64: dts: imx8mq-librem5: Mark charger IRQ as High-Z ... Link: https://lore.kernel.org/r/20210204120150.26186-5-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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