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path: root/drivers/clk/ingenic/cgu.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2022-05-18clk: ingenic: Allow specifying common clock flagsAidan MacDonald1-0/+3
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil1-0/+3
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil1-4/+3
2021-06-27clk: Support bypassing dividersPaul Cercueil1-0/+2
2020-05-28clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)1-0/+4
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds1-0/+4
2019-06-25clk: ingenic: Add missing header in cgu.hPaul Cercueil1-0/+1
2019-06-07clk: ingenic: Add support for divider tablesPaul Cercueil1-0/+3
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner1-10/+1
2019-02-22clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil1-1/+1
2018-06-15docs: Fix some broken referencesMauro Carvalho Chehab1-1/+1
2018-06-01clk: ingenic: Support specifying "wait for clock stable" delayPaul Cercueil1-0/+2
2018-06-01clk: ingenic: Add support for clocks whose gate bit is invertedPaul Cercueil1-0/+2
2018-01-18clk: ingenic: support PLLs with no bypass bitPaul Cercueil1-0/+2
2018-01-18clk: ingenic: Use const pointer to clk_ops in structPaul Cercueil1-1/+1
2017-11-03Update MIPS email addressesPaul Burton1-1/+1
2016-05-12clk: ingenic: Allow divider value to be dividedHarvey Hunt1-1/+5
2015-06-21clk: ingenic: add driver for Ingenic SoC CGU clocksPaul Burton1-0/+223