Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2017-11-02 | clk: mediatek: add the option for determining PLL source clock | 1 | -1/+4 | |
2017-11-02 | clk: mediatek: Add MT2712 clock support | 1 | -2/+11 | |
2016-11-08 | clk: mediatek: Add MT2701 clock support | 1 | -0/+1 | |
2016-08-18 | clk: mediatek: remove __init from clk registration functions | 1 | -1/+1 | |
2015-10-01 | clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS | 1 | -6/+1 | |
2015-07-28 | clk: mediatek: Add MT8173 MMPLL change rate support | 1 | -3/+15 | |
2015-07-28 | clk: mediatek: Fix calculation of PLL rate settings | 1 | -2/+2 | |
2015-07-28 | clk: mediatek: Fix PLL registers setting flow | 1 | -9/+12 | |
2015-05-19 | clk: mediatek: Initialize clk_init_data | 1 | -1/+1 | |
2015-05-05 | clk: mediatek: Add initial common clock support for Mediatek SoCs. | 1 | -0/+332 |