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path: root/drivers/clk/renesas/rcar-gen3-cpg.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-10-08clk: renesas: cpg-lib: Move RPC clock registration to the libraryWolfram Sang1-87/+2
2021-05-11clk: renesas: rcar-gen3: Add boost support to Z clocksGeert Uytterhoeven1-4/+20
2021-05-11clk: renesas: rcar-gen3: Add custom clock for PLLsGeert Uytterhoeven1-19/+128
2021-05-11clk: renesas: rcar-gen3: Increase Z clock accuracyGeert Uytterhoeven1-2/+2
2021-05-11clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/Geert Uytterhoeven1-1/+1
2021-05-11clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate()Geert Uytterhoeven1-2/+1
2021-05-11clk: renesas: rcar-gen3: Make cpg_z_clk.mask u32Geert Uytterhoeven1-1/+1
2021-05-11clk: renesas: rcar-gen3: Update Z clock rate formula in commentsGeert Uytterhoeven1-1/+2
2021-03-30clk: renesas: Zero init clk_init_dataGeert Uytterhoeven1-1/+1
2021-01-12clk: renesas: rcar-gen3: Factor out CPG libraryWolfram Sang1-251/+1
2021-01-12clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clockWolfram Sang1-9/+10
2020-12-10clk: renesas: r8a774c0: Add RPC clocksLad Prabhakar1-0/+28
2020-10-26clk: renesas: rcar-gen3: Remove stp_ck handling for SDHIWolfram Sang1-26/+25
2019-12-20clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocksSergei Shtylyov1-2/+4
2019-10-21clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()Geert Uytterhoeven1-7/+12
2019-10-21clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()Geert Uytterhoeven1-8/+14
2019-10-01clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()Geert Uytterhoeven1-4/+8
2019-10-01clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()Geert Uytterhoeven1-14/+5
2019-10-01clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()Geert Uytterhoeven1-3/+3
2019-10-01clk: renesas: rcar-gen3: Improve arithmetic divisionsGeert Uytterhoeven1-2/+2
2019-04-11clk: renesas: rcar-gen3: Remove unused variableStephen Boyd1-1/+0
2019-04-04clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return valueTakeshi Kihara1-16/+14
2019-04-02clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parentsSimon Horman1-2/+2
2019-04-02clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2Simon Horman1-1/+0
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offsetSimon Horman1-11/+4
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisorTakeshi Kihara1-9/+15
2019-03-18clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()Geert Uytterhoeven1-6/+6
2019-02-05clk: renesas: rcar-gen3: Add RPC clocksSergei Shtylyov1-0/+101
2019-01-25clk: renesas: rcar-gen3: Add spinlockSergei Shtylyov1-0/+8
2019-01-25clk: renesas: rcar-gen3: Factor out cpg_reg_modify()Sergei Shtylyov1-18/+20
2018-12-14Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and 'clk-rockchip' into clk-nextStephen Boyd1-22/+33
2018-12-10clk: renesas: Remove usage of CLK_IS_BASICStephen Boyd1-1/+1
2018-12-07clk: renesas: rcar-gen3: Add HS400 quirk for SD clockNiklas Söderlund1-7/+26
2018-12-07clk: renesas: rcar-gen3: Add documentation for SD clocksNiklas Söderlund1-5/+5
2018-12-07clk: renesas: rcar-gen3: Set state when registering SD clocksNiklas Söderlund1-12/+4
2018-10-18Merge branch 'clk-renesas' into clk-nextStephen Boyd1-9/+31
2018-08-30clk: renesas: use SPDX identifier for Renesas driversWolfram Sang1-4/+1
2018-08-27clk: renesas: rcar-gen3: Add support for mode pin clock selectionGeert Uytterhoeven1-6/+4
2018-08-27clk: renesas: rcar-gen3: Add support for RCKSEL clock selectionGeert Uytterhoeven1-3/+20
2018-08-27clk: renesas: rcar-gen3: Add support for OSC EXTAL predividerGeert Uytterhoeven1-0/+7
2018-03-21clk: renesas: rcar-gen3: Always use readl()/writel()Geert Uytterhoeven1-7/+7
2018-02-12clk: renesas: rcar-gen3: Add Z2 clock divider supportTakeshi Kihara1-6/+16
2018-02-12clk: renesas: rcar-gen3: Add Z clock divider supportTakeshi Kihara1-0/+133
2017-10-20clk: renesas: rcar-gen3: Restore R clock during resumeGeert Uytterhoeven1-2/+11
2017-10-20clk: renesas: rcar-gen3: Restore SDHI clocks during resumeGeert Uytterhoeven1-13/+50
2017-10-20clk: renesas: cpg-mssr: Add support to restore core clocks during resumeGeert Uytterhoeven1-1/+2
2017-08-16clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocksGeert Uytterhoeven1-1/+19
2017-08-16clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven1-0/+2
2017-07-19clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div tableWolfram Sang1-26/+20
2017-07-19clk: renesas: rcar-gen3-cpg: Drop superfluous variableWolfram Sang1-2/+1