| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-12-01 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux |   Linus Torvalds | 2 | -11/+16 |
| 2019-11-05 | clk: sunxi-ng: h3: Export MBUS clock |   Jernej Skrabec | 1 | -4/+0 |
| 2019-10-29 | clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18 |   Colin Ian King | 1 | -1/+1 |
| 2019-10-02 | clk: sunxi-ng: h6: Allow GPU to change parent rate | Jernej Skrabec | 1 | -1/+1 |
| 2019-09-30 | clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL | Jernej Skrabec | 1 | -6/+15 |
| 2019-09-19 | Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' into clk-next |   Stephen Boyd | 4 | -14/+255 |
| 2019-08-21 | clk: sunxi-ng: h6: Allow I2S to change parent rate | Jernej Skrabec | 1 | -4/+4 |
| 2019-08-16 | clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered | Stephen Boyd | 1 | -2/+3 |
| 2019-08-12 | clk: sunxi-ng: v3s: add Allwinner V3 support |   Icenowy Zheng | 2 | -3/+227 |
| 2019-08-12 | clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks | Icenowy Zheng | 1 | -0/+3 |
| 2019-07-22 | clk: sunxi-ng: v3s: add the missing PLL_DDR1 | Icenowy Zheng | 2 | -6/+19 |
| 2019-07-17 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux | Linus Torvalds | 16 | -221/+397 |
| 2019-06-24 | Merge tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner | Stephen Boyd | 16 | -220/+396 |
| 2019-06-22 | clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE |   Chen-Yu Tsai | 1 | -14/+23 |
| 2019-06-22 | clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE | Chen-Yu Tsai | 1 | -12/+20 |
| 2019-06-22 | clk: sunxi-ng: gate: Add macros for referencing local clock parents | Chen-Yu Tsai | 1 | -0/+53 |
| 2019-06-22 | clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -1/+1 |
| 2019-06-22 | clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -25/+44 |
| 2019-06-22 | clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -15/+26 |
| 2019-06-22 | clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -10/+19 |
| 2019-06-18 | clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -1/+1 |
| 2019-06-18 | clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -10/+19 |
| 2019-06-18 | clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -17/+29 |
| 2019-06-18 | clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -10/+19 |
| 2019-06-18 | clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -12/+22 |
| 2019-06-18 | clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -12/+22 |
| 2019-06-18 | clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -14/+25 |
| 2019-06-18 | clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -12/+22 |
| 2019-06-18 | clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR | Chen-Yu Tsai | 1 | -14/+25 |
| 2019-06-18 | clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_* | Chen-Yu Tsai | 1 | -40/+25 |
| 2019-06-18 | clk: sunxi-ng: switch to of_clk_hw_register() for registering clks | Chen-Yu Tsai | 1 | -1/+1 |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 |   Thomas Gleixner | 28 | -252/+28 |
| 2019-06-05 | clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register |   Ondrej Jirman | 1 | -1/+1 |
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 | Thomas Gleixner | 15 | -150/+15 |
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 | Thomas Gleixner | 13 | -65/+13 |
| 2019-05-21 | treewide: Add SPDX license identifier - Makefile/Kconfig | Thomas Gleixner | 1 | -0/+1 |
| 2019-05-15 | clk: Remove io.h from clk-provider.h | Stephen Boyd | 26 | -0/+26 |
| 2019-05-07 | Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next | Stephen Boyd | 2 | -3/+3 |
| 2019-05-07 | Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' and 'clk-qoriq' into clk-next | Stephen Boyd | 6 | -13/+23 |
| 2019-05-01 | clk: sunxi-ng: Use the correct style for SPDX License Identifier |   Nishad Kamdar | 2 | -3/+3 |
| 2019-04-10 | clk: sunxi-ng: sun5i: Export the MBUS clock |   Maxime Ripard | 1 | -4/+0 |
| 2019-04-09 | clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk | Chen-Yu Tsai | 1 | -2/+3 |
| 2019-04-04 | clk: sunxi-ng: nkmp: Explain why zero width check is needed | Jernej Skrabec | 1 | -0/+6 |
| 2019-04-04 | clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate | Jernej Skrabec | 1 | -3/+3 |
| 2019-04-03 | clk: sunxi-ng: h6: Preset hdmi-cec clock parent | Jernej Skrabec | 1 | -0/+11 |
| 2019-04-03 | clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0) | Jernej Skrabec | 1 | -5/+13 |
| 2019-03-18 | clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset | Icenowy Zheng | 1 | -1/+1 |
| 2019-03-18 | clk: sunxi-ng: Allow DE clock to set parent rate | Jernej Skrabec | 3 | -3/+5 |
| 2019-03-08 | Merge branches 'clk-optional', 'clk-devm-clkdev-register', 'clk-allwinner', 'clk-meson' and 'clk-renesas' into clk-next | Stephen Boyd | 1 | -1/+1 |
| 2019-01-28 | clk: sunxi: A31: Fix wrong AHB gate number |   Andre Przywara | 1 | -2/+2 |
