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Jason A. Donenfeld
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path:
root
/
drivers
/
clk
/
tegra
/
clk-tegra20.c
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2018-11-08
clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
Dmitry Osipenko
1
-0
/
+10
2018-11-08
clk: tegra20: Turn EMC clock gate into divider
Dmitry Osipenko
1
-10
/
+26
2018-05-18
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
Dmitry Osipenko
1
-1
/
+31
2018-05-18
clk: tegra20: Correct parents of CDEV1/2 clocks
Dmitry Osipenko
1
-4
/
+2
2018-05-18
clk: tegra20: Add DEV1/DEV2 OSC dividers
Dmitry Osipenko
1
-0
/
+14
2018-03-12
clk: tegra: Specify VDE clock rate
Dmitry Osipenko
1
-0
/
+1
2018-03-12
clk: tegra20: Correct PLL_C_OUT1 setup
Dmitry Osipenko
1
-3
/
+3
2018-03-12
clk: tegra: Mark HCLK, SCLK and EMC as critical
Dmitry Osipenko
1
-13
/
+10
2017-11-01
clk: tegra: Bump SCLK clock rate to 216 MHz
Dmitry Osipenko
1
-1
/
+1
2017-11-01
clk: tegra: Use common definition of APBDMA clock gate
Dmitry Osipenko
1
-5
/
+1
2017-11-01
clk: tegra: Add AHB DMA clock entry
Dmitry Osipenko
1
-0
/
+1
2017-10-19
clk: tegra: Use tegra_clk_register_periph_data()
Thierry Reding
1
-3
/
+1
2016-04-28
treewide: Fix typos in printk
Masanari Iida
1
-1
/
+1
2016-03-02
clk: tegra: Remove CLK_IS_ROOT
Stephen Boyd
1
-6
/
+4
2015-11-20
clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate
Rhyland Klein
1
-72
/
+78
2015-11-20
clk: tegra: pll: Don't unconditionally set LOCK flags
Rhyland Klein
1
-8
/
+10
2015-11-20
clk: tegra: Constify pdiv-to-hw mappings
Thierry Reding
1
-1
/
+1
2015-11-18
clk: tegra: Format tables consistently
Thierry Reding
1
-143
/
+134
2015-11-18
clk: tegra: Miscellaneous coding style cleanups
Thierry Reding
1
-3
/
+2
2015-07-20
clk: tegra: Properly include clk.h
Stephen Boyd
1
-1
/
+0
2014-11-26
clk: tegra: Implement memory-controller clock
Thierry Reding
1
-1
/
+7
2014-02-17
clk: tegra: Add missing Tegra20 fuse clks
Peter De Schrijver
1
-0
/
+2
2013-12-11
clk: tegra: remove bogus PCIE_XCLK
Stephen Warren
1
-6
/
+0
2013-12-11
clk: tegra: implement a reset driver
Stephen Warren
1
-1
/
+2
2013-11-26
clk: tegra: add FUSE clock device
Alexandre Courbot
1
-0
/
+1
2013-11-26
clk: tegra: move tegra20 to common infra
Peter De Schrijver
1
-402
/
+255
2013-11-26
clk: tegra: move periph clocks to common file
Peter De Schrijver
1
-2
/
+2
2013-11-26
clk: tegra: move fields to tegra_clk_pll_params
Peter De Schrijver
1
-17
/
+27
2013-11-26
clk: tegra: common periph_clk_enb_refcnt and clks
Peter De Schrijver
1
-27
/
+9
2013-11-26
clk: tegra: simplify periph clock data
Peter De Schrijver
1
-138
/
+82
2013-08-19
clk: add CLK_SET_RATE_NO_REPARENT flag
James Hogan
1
-2
/
+4
2013-08-08
clk: tegra20: Fix incorrect placement of __initdata
Sachin Kamat
1
-1
/
+1
2013-05-31
clk: tegra: Use common of_clk_init function
Prashant Gaikwad
1
-1
/
+2
2013-05-20
clk: tegra: add ac97 controller clock
Lucas Stach
1
-0
/
+8
2013-05-20
clk: tegra: remove USB from clk init table
Lucas Stach
1
-3
/
+0
2013-05-04
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Linus Torvalds
1
-85
/
+99
2013-05-02
Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Linus Torvalds
1
-34
/
+2
2013-04-09
Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/fixes-non-critical
Arnd Bergmann
1
-34
/
+2
2013-04-04
clk: tegra: Add flags to tegra_clk_periph()
Peter De Schrijver
1
-1
/
+1
2013-04-04
clk: tegra: move from a lock bit idx to a lock mask
Peter De Schrijver
1
-10
/
+10
2013-04-04
clk: tegra: Add PLL post divider table
Peter De Schrijver
1
-0
/
+7
2013-04-04
clk: tegra: Refactor PLL programming code
Peter De Schrijver
1
-72
/
+72
2013-04-04
clk: tegra: defer application of init table
Stephen Warren
1
-1
/
+6
2013-04-04
clk: tegra: Fix cdev1 and cdev2 IDs
Prashant Gaikwad
1
-1
/
+1
2013-04-04
clk: tegra: Make gr2d and gr3d clocks children of pll_c
Thierry Reding
1
-0
/
+2
2013-04-04
Merge branch 'for-3.10/soc' into for-3.10/clk
Stephen Warren
1
-34
/
+2
2013-04-01
clk: tegra: Allow PLLE training to succeed
Thierry Reding
1
-1
/
+1
2013-03-11
clk: tegra: No 7.1 super clk dividers on Tegra20
Peter De Schrijver
1
-34
/
+2
2013-03-04
clk: Tegra: Remove duplicate smp_twd clock
Prashant Gaikwad
1
-1
/
+0
2013-02-13
clk: tegra: initialise parent of uart clocks
Laxman Dewangan
1
-2
/
+5
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