Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-08-20 | RISC-V: Remove CLINT related code from timer and arch | 1 | -15/+2 | |
2020-06-09 | clocksource/drivers/timer-riscv: Use per-CPU timer interrupt | 1 | -3/+40 | |
2020-01-04 | clocksource: riscv: add notrace to riscv_sched_clock | 1 | -1/+1 | |
2019-11-13 | riscv: add support for MMIO access to the timer registers | 1 | -4/+19 | |
2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | 1 | -4/+4 | |
2019-09-05 | riscv: don't use the rdtime(h) pseudo-instructions | 1 | -13/+4 | |
2019-08-06 | RISC-V: Remove per cpu clocksource | 1 | -4/+2 | |
2019-03-23 | clocksource/drivers/riscv: Fix clocksource mask | 1 | -3/+2 | |
2019-02-23 | clocksource/drivers/riscv: Add required checks during clock source init | 1 | -3/+20 | |
2018-12-18 | clocksource/drivers/riscv: Change name riscv_timer to timer-riscv | 1 | -0/+118 |