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path: root/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21 (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-06-08drm/amd/display: Revert "Fix clock table filling logic"Ilya Bakoulin1-51/+27
2021-05-19drm/amd/display: treat memory as a single-channel for asymmetric memory V3Hugo Hu1-2/+46
2021-05-10drm/amd/display: Handle potential dpp_inst mismatch with pipe_idxAnthony Wang1-3/+3
2021-05-10drm/amd/display: Fix clock table filling logicIlya Bakoulin1-27/+53
2021-05-10drm/amdgpu/dc: Revert commit "treat memory as a single-channel"Aric Cyr1-46/+2
2021-04-28drm/amd/display: Revert wait vblank on update dpp clockLewis Huang1-9/+1
2021-04-20drm/amd/display: treat memory as a single-channel for asymmetric memory v2Hugo Hu1-2/+46
2021-04-15drm/amd/display: wait vblank when stream enabled and update dpp clockLewis Huang1-1/+9
2021-04-09drm/amd/display: Populate socclk entries for dcn2.1Roman Li1-0/+13
2020-12-23drm/amd/display: always program DPPDTO unless not safe to lowerJake Wang1-6/+5
2020-12-23drm/amd/display: updated wm table for RenoirJake Wang1-8/+8
2020-12-23drm/amd/display: Update RN/VGH active display count workaroundMichael Strauss1-8/+1
2020-12-23drm/amd/display: change SMU repsonse timeout to 2s.Yongqiang Sun1-1/+1
2020-12-15drm/amd/display: updated wm table for RenoirJake Wang1-6/+6
2020-12-08drm/amd/display: Add wm table for RenoirSung Lee1-4/+89
2020-12-01drm/amd/display: Init clock value by current vbios CLKsBrandon Syu1-2/+11
2020-11-16drm/amd/display: Increase sr enter/exit in rn ddr4 watermark tableWyatt Wood1-2/+2
2020-11-16drm/amd/display: set dpp dto as per requested clk for lower case.Yongqiang Sun1-5/+23
2020-11-16drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1Sung Lee1-1/+2
2020-11-16drm/amd/display: Program dpp dto based on actual dpp clkYongqiang Sun1-3/+26
2020-11-10drm/amd/display: check actual clock value.Yongqiang Sun2-3/+14
2020-11-10drm/amd/display: update dpp dto phase and modulo.Yongqiang Sun1-4/+2
2020-10-26drm/amd/display: DCN2.1 Disable 48MHz Powerdown Debug OptionSung Lee1-1/+1
2020-09-29drm/amd/display: remove duplicate call to rn_vbios_smu_get_smu_version()Dirk Gouders1-1/+0
2020-09-15drm/amd/display: Check clock table returnRodrigo Siqueira1-2/+5
2020-08-26drm/amd/display: Send DISPLAY_OFF after power down on bootSung Lee1-0/+10
2020-07-14drm/amd/display: reduce sr_xxx_time by 3 us when ppt disableChiawen Huang3-3/+54
2020-07-08drm/amd/display: Request PHYCLK adjustment on PHY enable/disableJoshua Aberback1-6/+21
2020-07-02drm/amd/display: Handle SMU msg responseYongqiang Sun1-2/+38
2020-07-01drm/amd/display: Red screen observed on startupPeikang Zhang1-1/+2
2020-04-07drm/amd/display: Check for null fclk voltage when parsing clock tableMichael Strauss1-1/+1
2020-03-05drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU VersionsSung Lee1-0/+8
2020-02-25drm/amd/display: make some rn_clk_mgr structs and funcs staticAnthony Koo1-4/+4
2020-02-06drm/amd/display: Limit minimum DPPCLK to 100MHz.Yongqiang Sun1-0/+6
2020-02-06drm/amd/display: Add wm ranges to clk_mgrSung Lee1-3/+2
2020-02-06drm/amd/display: Use dcfclk to populate watermark rangesSung Lee1-7/+7
2020-01-16drm/amd/display: Update HDMI hang w/a to apply to all TMDS signalsMichael Strauss1-4/+6
2019-12-18drm/amd/display: Remove unneeded semicolonzhengbin1-1/+1
2019-12-18drm/amd/display: Lower DPP DTO only when safeSung Lee1-4/+4
2019-12-05drm/amd/display: Compare clock state member to determine optimization.Yongqiang Sun1-1/+17
2019-12-05drm/amd/display: update sr latency for renoir when using lpddr4Joseph Gravenor1-8/+8
2019-12-05drm/amd/display: update p-state latency for renoir when using lpddr4Joseph Gravenor1-4/+4
2019-12-05drm/amd/display: fix dprefclk and ss percentage reading on RNEric Yang1-13/+3
2019-12-05drm/amd/display: have two different sr and pstate latency tables for renoirJoseph Gravenor1-34/+80
2019-12-05drm/amd/display: populate bios integrated info for renoirJoseph Gravenor1-4/+6
2019-12-05drm/amd/display: rename core_dc to dcAnthony Koo1-3/+3
2019-12-05drm/amd/display: update sr and pstate latencies for RenoirEric Yang1-4/+12
2019-10-25drm/amd/display: Make clk mgr the only dto update pointNoah Abradjian1-1/+2
2019-10-25drm/amd/display: move wm ranges reporting to end of init hwEric Yang1-73/+76
2019-10-25drm/amd/display: move dispclk vco freq to clk mgr baseDmytro Laktyushkin2-13/+6
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