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path: root/drivers/gpu/drm/amd/include/asic_reg/gc (follow)
AgeCommit message (Expand)AuthorFilesLines
2019-08-02drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc headerXiaojie Yuan2-0/+41
2019-07-31drm/amd/include: add define of TCP_EDC_CNT_NEWDennis Li1-0/+2
2019-07-31drm/amd/include: add bitfield define for EDC registersDennis Li1-0/+157
2019-06-20drm/amdgpu: add GC 10.1 register headers (v4)Hawking Zhang3-0/+61330
2019-05-24drm/amdgpu: add EDC counter registerJames Zhu1-0/+31
2018-10-10drm/amdgpu: add CP_DEBUG register definition for GC9.0Tao Zhou1-0/+2
2018-09-10drm/amd/include: update the bitfield define for PF_MAX_REGIONShaoyun Liu1-2/+2
2018-03-21drm/amd/include: Add ip header files for vega12.Feifei Xu2-0/+38657
2018-03-07drm/amd/amdgpu: re-add missing GC 9.1 and SDMA0 4.1 sh_mask header filesTom St Denis1-0/+31150
2017-12-13drm/amdgpu: remove some old gc 9.x registersAlex Deucher4-80/+0
2017-12-06drm/amd/include:cleanup raven1 gc header files.Feifei Xu1-0/+7491
2017-12-06drm/amd/include:cleanup vega10 gc header files.Feifei Xu3-0/+40971