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path: root/drivers/gpu/drm/i915/display/intel_dpll.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-09-29drm/i915: split the dpll clock compute out from display vtable.Dave Airlie1-8/+8
2021-09-15drm/i915: s/pipe/transcoder/ when dealing with PIPECONF/TRANSCONFVille Syrjälä1-6/+6
2021-09-15drm/i915: Flatten hsw_crtc_compute_clock()Ville Syrjälä1-9/+11
2021-08-25drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll()Ville Syrjälä1-0/+3
2021-08-25drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as wellVille Syrjälä1-2/+2
2021-08-25drm/i915: Call {vlv,chv}_prepare_pll() from {vlv,chv}_enable_pll()Ville Syrjälä1-126/+119
2021-08-25drm/i915: Program DPLL P1 dividers consistentlyVille Syrjälä1-39/+41
2021-08-25drm/i915: Remove the 'reg' local variableVille Syrjälä1-9/+9
2021-08-25drm/i915: Clean up variable names in old dpll functionsVille Syrjälä1-75/+76
2021-08-25drm/i915: Clean dpll calling conventionVille Syrjälä1-74/+68
2021-08-25drm/i915: Constify struct dpll all overVille Syrjälä1-23/+35
2021-08-25drm/i915: Extract ilk_update_pll_dividers()Ville Syrjälä1-8/+17
2021-08-25drm/i915: Set output_types to EDP for vlv/chv DPLL forcingVille Syrjälä1-0/+1
2021-07-29drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper1-5/+7
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä1-0/+1
2021-04-14drm/i915/display: rename display version macrosLucas De Marchi1-1/+1
2021-04-14drm/i915/display: Eliminate IS_GEN9_{BC,LP}Matt Roper1-4/+2
2021-03-23drm/i915/display: Eliminate most usage of INTEL_GEN()Matt Roper1-6/+6
2021-02-08drm/i915: migrate pll enable/disable code to intel_dpll.[ch]Dave Airlie1-0/+509
2021-01-16drm/i915: refactor pll code out into intel_dpll.cDave Airlie1-0/+1363
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