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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2017-10-17drm/i915: Use a mask when applying WaProgramL3SqcReg1DefaultOscar Mateo1-0/+1
2017-10-13drm/i915: Fix DP_AUX_CH_CTL_TIME_OUT namingJames Ausmus1-1/+1
2017-10-10drm/i915: Cleanup South Error InterruptsMika Kahola1-3/+0
2017-10-10drm/i915: Parametrize CBR_DPLLBMD_PIPE definesVille Syrjälä1-2/+1
2017-10-07drm/i915: enable IPS bit for 64K pagesMatthew Auld1-0/+3
2017-10-04drm/i915/preempt: Default to disabled mid-command preemption levelsMichał Winiarski1-0/+6
2017-10-03drm/i915/glk, cnl: Implement WaDisableScalarClockGatingImre Deak1-0/+10
2017-09-28drm/i915/psr: Set frames before SU entry for psr2vathsala nagaraju1-1/+1
2017-09-26drm/i915/cnl: Add support slice/subslice/eu configsBen Widawsky1-0/+8
2017-09-26drm/i915: Enable scanline read based on frame timestampsUma Shankar1-0/+9
2017-09-19drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlugRodrigo Vivi1-0/+2
2017-09-14drm/i915/cnl: Change the macro name to DPLL_CFGCR0_DCO_FRACTION_SHIFTManasi Navare1-1/+1
2017-09-14drm/i915: Switch over to the LLC/eLLC hotspot avoidance hash mode for CCSVille Syrjälä1-1/+7
2017-09-12drm/i915: Name the IPS_PCODE_CONTROL bitVille Syrjälä1-0/+2
2017-09-12drm/i915: Nuke some bogus tabs from the pcode definesVille Syrjälä1-3/+3
2017-09-08drm/i915: Make PAT macros more robustMichal Wajdeczko1-1/+1
2017-09-07drm/i915/bxt+: Enable IPC supportKumar, Mahesh1-0/+1
2017-09-06drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)Rodrigo Vivi1-0/+1
2017-09-06drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glkRodrigo Vivi1-0/+3
2017-09-05drm/i915/cnp: Wa 1181: Fix Backlight issueRodrigo Vivi1-0/+1
2017-08-30drm/i915/cnl: WaDisableI2mCycleOnWRPortRodrigo Vivi1-0/+1
2017-08-30drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFixRodrigo Vivi1-0/+1
2017-08-25drm/i915: Fix FBC cfb stride programming for non X-tiled FBPraveen Paneri1-0/+4
2017-08-23drm/i915/cnl: WaForceContextSaveRestoreNonCoherentRodrigo Vivi1-0/+1
2017-08-23drm/i915/cnl: WaPushConstantDereferenceHoldDisableOscar Mateo1-0/+1
2017-08-18drm/i915/cnl: Apply large line width optimizationRodrigo Vivi1-0/+1
2017-08-18drm/i915/cnl: Introduce initial Cannonlake Workarounds.Rodrigo Vivi1-0/+6
2017-08-15drm/i915/cnl: Setup PAT Index.Rodrigo Vivi1-0/+1
2017-08-15drm/i915/hsw+: Add support for multiple power well regsImre Deak1-7/+25
2017-08-10drm/i915: add register macro definition style guideJani Nikula1-0/+91
2017-08-10drm/i915: enum i915_power_well_id is not proper kernel-docJani Nikula1-1/+1
2017-08-10drm/i915: Add render decompression supportVille Syrjälä1-0/+23
2017-08-09drm/i915/psr: Preserve SRD_CTL bit 29 on PSR initJim Bride1-0/+1
2017-08-03drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interfaceLionel Landwerlin1-3/+67
2017-08-03drm/i915: reorder NOA register definition to follow addressesLionel Landwerlin1-106/+106
2017-07-27drm/i915: cleanup the CHICKEN_MISC_2 (re)definitionsPaulo Zanoni1-5/+3
2017-07-27drm/i915: prepare pipe for YCBCR420 outputShashank Sharma1-0/+3
2017-07-27drm/i915/hsw+: Add has_fuses power well attributeImre Deak1-4/+10
2017-07-27drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macrosImre Deak1-5/+3
2017-07-27drm/i915/hsw, bdw: Add an ID for the global display power wellImre Deak1-0/+6
2017-07-27drm/i915/gen2: Add an ID for the display pipes power wellImre Deak1-0/+6
2017-07-27drm/i915: Unify power well ID enumsImre Deak1-14/+28
2017-07-27drm/i915/chv: Add unique power well ID for the pipe A power wellImre Deak1-0/+2
2017-07-07drm/i915/cnl: Get DDI clock based on PLLs.Rodrigo Vivi1-0/+2
2017-07-07drm/i915/cnl: Inherit RPS stuff from previous platforms.Rodrigo Vivi1-2/+2
2017-06-30drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI Vswing ProgrammingNavare, Manasi D1-1/+1
2017-06-19drm/i915/cnl: Fix RMW on ddi vswing sequence.Rodrigo Vivi1-0/+9
2017-06-14drm/i915/perf: Add OA unit support for Gen 8+Robert Bragg1-0/+22
2017-06-12drm/i915/cnl: Implement voltage swing sequence.Rodrigo Vivi1-0/+1
2017-06-12drm/i915/cnl: Add registers related to voltage swing sequences.Rodrigo Vivi1-0/+140
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