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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2020-09-15drm/i915: Nuke the redundant TC/TBT HPD bit definesVille Syrjälä1-24/+12
2020-09-11drm/i915: Nuke dpio_phy_iosf_port[]Ville Syrjälä1-1/+0
2020-08-26drm/i915/gt: Implement WA_1406941453Clint Taylor1-0/+1
2020-08-17drm/i915/display: Implement WA 1408330847José Roberto de Souza1-0/+1
2020-08-17drm/i915/tgl: Set subplatformsJosé Roberto de Souza1-0/+6
2020-08-17drm/i915/tgl: Fix TC-cold block/unblock sequenceImre Deak1-2/+2
2020-08-17Revert "drm/i915/rkl: Add Wa_14011224835 for PHY B initialization"Matt Roper1-12/+1
2020-08-17drm/i915: Implement WA 14011294188José Roberto de Souza1-0/+1
2020-08-17drm/i915/rkl: Add Wa_14011224835 for PHY B initializationMatt Roper1-1/+12
2020-08-17drm/i915/rkl: Handle HTIMatt Roper1-0/+6
2020-08-17drm/i915/rkl: Add DPLL4 supportMatt Roper1-2/+4
2020-08-17drm/i915/rkl: Handle new DPCLKA_CFGCR0 layoutMatt Roper1-0/+6
2020-08-17drm/i915/display: Implement HOBLJosé Roberto de Souza1-0/+2
2020-07-14drm/i915/dg1: add support for the master unit interruptLucas De Marchi1-0/+4
2020-07-07drm/i915/display: Implement new combo phy initialization stepJosé Roberto de Souza1-0/+9
2020-07-06drm/i915: Fix spelling mistake in i915_reg.hFlavio Suligoi1-2/+2
2020-07-03drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865Ville Syrjälä1-0/+1
2020-06-30drm/i915: Add PSR2 selective fetch registersJosé Roberto de Souza1-5/+63
2020-06-30drm/i915/fbc: Parametrize FBC_CONTROLVille Syrjälä1-7/+11
2020-06-26drm/i915/gen12: implement Wa_14011508470Matt Atwood1-0/+6
2020-06-25Merge drm/drm-next into drm-intel-next-queuedJani Nikula1-1/+1
2020-06-16drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workaroundsChris Wilson1-1/+1
2020-06-11drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workaroundsChris Wilson1-1/+1
2020-06-10Merge branch 'uaccess.i915' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfsLinus Torvalds1-1/+1
2020-06-09drm/i915/rkl: RKL uses ABOX0 for pixel transfersMatt Roper1-7/+17
2020-06-07drm/i915/psr: Program default IO buffer Wake and Fast WakeGwan-gyeong Mun1-19/+33
2020-06-04drm/i915/rkl: Setup ports/physMatt Roper1-1/+3
2020-06-04drm/i915/tgl: Implement WA_16011163337Clint Taylor1-0/+2
2020-06-01drm/i915: Add Plane color encoding support for YCBCR_BT2020Kishore Kadiyala1-1/+1
2020-05-20drm/i915/rkl: Limit number of universal planes to 5Matt Roper1-0/+5
2020-05-19drm/i915: Read out hrawclk on all gen3+ platformsVille Syrjälä1-1/+2
2020-05-19drm/i915: Fix 400 MHz FSB readout on elkVille Syrjälä1-5/+1
2020-05-07drm/i915/gen12: Add aux table invalidate for all enginesMika Kuoppala1-0/+6
2020-05-07drm/i915/gen12: Invalidate aux table entries forciblyMika Kuoppala1-0/+2
2020-05-05drm/i915/icp: Add Wa_14010685332Matt Roper1-0/+1
2020-05-05drm/i915: Added required new PCode commandsStanislav Lisovskiy1-0/+4
2020-05-01i915: switch copy_perf_config_registers_or_number() to unsafe_put_user()Al Viro1-1/+1
2020-04-30drm/i915/selftests: Add tiled blits selftestZbigniew Kempczyński1-0/+2
2020-04-25drm/i915: Use indirect ctx bb to mend CMD_BUF_CCTLMika Kuoppala1-0/+1
2020-04-24drm/i915/gt: Use the RPM config register to determine clk frequenciesChris Wilson1-25/+0
2020-04-20drm/i915/selftests: Check RPS controlsChris Wilson1-0/+1
2020-04-20drm/i915: fix Sphinx build duplicate label warningJani Nikula1-2/+2
2020-04-17drm/i915/tc/tgl: Implement TC cold sequencesJosé Roberto de Souza1-0/+4
2020-04-17drm/i915/tc/icl: Implement TC cold sequencesJosé Roberto de Souza1-0/+1
2020-04-17drm/i915/display: Enable DP Display Audio WAUma Shankar1-0/+16
2020-04-16Merge tag 'topic/phy-compliance-2020-04-08' of git://anongit.freedesktop.org/drm/drm-misc into drm-intel-next-queuedJoonas Lahtinen1-0/+18
2020-04-16drm/i915: Add YUV444 packed format support for skl+Stanislav Lisovskiy1-1/+1
2020-04-08drm/i915/dp: Register definition for DP compliance registerAnimesh Manna1-0/+18
2020-04-07drm/i915/gt: Yield the timeslice if caught waiting on a user semaphoreChris Wilson1-0/+1
2020-04-03drm/i915: Implement port sync for SKL+Ville Syrjälä1-0/+3
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