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path: root/drivers/gpu/drm/i915/intel_uncore.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2015-02-09drm/i915: Squelch overzealous uncore reset WARN_ONMika Kuoppala1-1/+8
2015-01-30drm/i915: Don't do posting reads on getting forcewakeMika Kuoppala1-1/+0
2015-01-30drm/i915: Do uncore early sanitize after domain initMika Kuoppala1-8/+30
2015-01-27drm/i915: Enum forcewake domains and domain identifiersMika Kuoppala1-22/+25
2015-01-27drm/i915: Rename the forcewake get/put functionsMika Kuoppala1-16/+28
2015-01-27drm/i915: Make vlv and chv forcewake put generic.Mika Kuoppala1-11/+5
2015-01-27drm/i915: Consolidate forcewake codeMika Kuoppala1-264/+207
2015-01-27drm/i915: Reduce duplicated forcewake logicChris Wilson1-262/+183
2015-01-27drm/i915: Skip uncore lock on earlier gensChris Wilson1-67/+91
2015-01-27drm/i915: Assert that runtime pm is active on user fw accessChris Wilson1-53/+23
2015-01-27drm/i915: Rebalance runtime pm vs forcewakeChris Wilson1-12/+6
2014-12-15drm/i915: Forcewake Register Range changes for CHVDeepak S1-7/+4
2014-12-15drm/i915: Use BUILD_BUG if possible in the i915 WARN_ONDaniel Vetter1-2/+2
2014-12-03drm/i915/skl: Update in Gen9 multi-engine forcewake rangeAkash Goel1-4/+8
2014-12-03drm/i915: Disable crtcs gracefully before GPU reset on gen3/4Ville Syrjälä1-2/+0
2014-12-03drm/i915: Implement GPU reset for g33Ville Syrjälä1-1/+11
2014-12-03drm/i915: Implement GPU reset for 915/945Ville Syrjälä1-12/+12
2014-12-03drm/i915: Fix gen4 GPU resetVille Syrjälä1-27/+14
2014-12-03drm/i915: Only warn the first time we attempt to mmio whilst suspendedChris Wilson1-2/+2
2014-11-20drm/i915: Gen9 shadowed registersZhe Wang1-1/+25
2014-11-20drm/i915/skl: Gen9 multi-engine forcewakeZhe Wang1-0/+115
2014-11-17drm/i915: Drop WaRsForcewakeWaitTC0:vlvVille Syrjälä1-4/+0
2014-11-17drm/i915: Drop the HSW special case from __gen6_gt_wait_for_thread_c0()Ville Syrjälä1-8/+2
2014-11-14drm/i915: Wait thread status on gen8+ fw sequenceMika Kuoppala1-2/+1
2014-11-07Revert "drm/i915/vlv: Remove check for Old Ack during forcewake"Mika Kuoppala1-7/+10
2014-11-07drm/i915/skl: Gen9 ForcewakeZhe Wang1-1/+174
2014-10-24drm/i915: check for GT faults in all resume handlers and driver load timeImre Deak1-2/+11
2014-10-24drm/i915: use macros to assign mmio access functionsYu Zhang1-48/+30
2014-09-30Merge branch 'topic/skl-stage1' into drm-intel-next-queuedDaniel Vetter1-1/+1
2014-09-24drm/i915/skl: Allow the reg_read ioctl to return RCS_TIMESTAMPDamien Lespiau1-1/+1
2014-09-19drm/i915/vlv: Remove check for Old Ack during forcewakeDeepak S1-10/+7
2014-09-03drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake codeVille Syrjälä1-3/+3
2014-07-23drm/i915: BDW can also detect unclaimed registersPaulo Zanoni1-0/+3
2014-07-23drm/i915: reorganize the unclaimed register detection codePaulo Zanoni1-7/+20
2014-07-08drm/i915: Emphasize that ctx->id is merely a user handleOscar Mateo1-1/+1
2014-06-18Merge branch 'topic/soix' into drm-intel-next-queuedDaniel Vetter1-1/+1
2014-06-13drm/i915: preserve user forcewake over system suspend/resumeImre Deak1-7/+3
2014-06-13drm/i915: fix possible refcount leak when resetting forcewakeImre Deak1-1/+2
2014-06-12drm/i915: leave rc6 enabled at suspend time v4Jesse Barnes1-1/+1
2014-06-11drm/i915: Simplify intel_gpu_resetRobert Beckett1-12/+10
2014-06-11drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHVVille Syrjälä1-3/+4
2014-06-11drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0Ville Syrjälä1-2/+2
2014-06-11drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuffDeepak S1-17/+118
2014-06-06Merge tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-intel into drm-nextDave Airlie1-18/+3
2014-06-05Merge commit '9e9a928eed8796a0a1aaed7e0b676db86ba84594' into drm-nextDave Airlie1-0/+2
2014-06-05drm/i915/vlv: drop power well enable in uncore_sanitizeJesse Barnes1-18/+0
2014-06-05drm/i915: Disable gpu reset on i965g/gmDaniel Vetter1-0/+3
2014-05-22drm/i915: s/i915_hw_context/intel_contextOscar Mateo1-1/+1
2014-05-22drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elkVille Syrjälä1-1/+35
2014-05-20drm/i915: Clear GDSR after reset on ILKVille Syrjälä1-2/+8
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