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path: root/drivers/gpu/drm/mediatek/mtk_drm_ddp.c (follow)
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2021-02-04drm/mediatek: Rename file mtk_drm_ddp to mtk_mutexCK Hu1-464/+0
After mmsys routing function is moved out of mtk_drm_ddp.c, mtk_drm_ddp.c has only mtk mutex function, so rename it to match the function in it. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2020-11-08drm/mediatek: Add DDP support for MT8167Fabien Parent1-0/+47
Add DDP support for MT8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2020-04-13soc / drm: mediatek: Move routing control to mmsys deviceEnric Balletbo i Serra1-256/+0
Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). Those functions will allow DRM driver and others to control the data path routing. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com> Tested-by: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13drm/mediatek: Omit warning on probe defersMatthias Brugger1-1/+2
It can happen that the mmsys clock drivers aren't probed before the platform driver gets invoked. The platform driver used to print a warning that the driver failed to get the clocks. Omit this error on the defered probe path. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-10-09drm/mediatek: add no_clk into ddp private dataCK Hu1-6/+9
Mutex has no clock in some SoC, so add no_clk in private data and get clock according to no_clk. Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add mutex sof register offset into ddp private dataYongqiang Niu1-3/+10
mutex sof register offset will be private data of ddp Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add mutex sof into ddp private dataYongqiang Niu1-8/+35
mutex sof will be ddp private data Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add mutex mod register offset into ddp private dataYongqiang Niu1-8/+16
mutex mod register offset will be private data of ddp. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add mutex mod into ddp private dataYongqiang Niu1-11/+30
except mutex mod, mutex mod reg,mutex sof reg, and mutex sof id will be ddp private data Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-03drm/mediatek: implement connection from BLS to DPI0Bibby Hsieh1-1/+13
Modify display driver to support connection from BLS to DPI. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-08-27drm/mediatek: fix connection from RDMA2 to DSI1Stu Hsieh1-1/+1
This patch fix connection from RDMA2 to DSI1 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-08-27drm/mediatek: add connection from RDMA2 to DSI0Stu Hsieh1-0/+4
This patch add connection from RDMA2 to DSI0 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-08-27drm/mediatek: add connection from RDMA1 to DSI0Stu Hsieh1-0/+4
This patch add connection from RDMA1 to DSI0 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-08-27drm/mediatek: add connection from RDMA0 to DSI1Stu Hsieh1-0/+4
This patch add connection from RDMA0 to DSI1 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-08-27drm/mediatek: add connection from RDMA0 to DPI1Stu Hsieh1-0/+4
This patch add connection from RDMA0 to DPI1 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-28drm/mediatek: Add support for mediatek SOC MT2712stu.hsieh@mediatek.com1-0/+39
This patch add support for the Mediatek MT2712 DISP subsystem. There are two OVL engine and three disp output in MT2712. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add DSI3 support for mutexstu.hsieh@mediatek.com1-0/+5
This patch add the DSI3 support for mutex Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add DSI2 support for mutexstu.hsieh@mediatek.com1-0/+5
This patch add the DSI2 support for mutex Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add DPI1 support for mutexstu.hsieh@mediatek.com1-0/+5
This patch add the DPI1 support for mutex Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA2 to DSI3stu.hsieh@mediatek.com1-0/+8
This patch add the connection from RDMA2 to DSI3 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA2 to DSI2stu.hsieh@mediatek.com1-0/+8
This patch add the connection from RDMA2 to DSI2 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA2 to DSI1stu.hsieh@mediatek.com1-0/+8
This patch add the connection from RDMA2 to DSI1 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA2 to DPI1stu.hsieh@mediatek.com1-0/+8
This patch add the connection from RDMA2 to DPI1 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA2 to DPI0stu.hsieh@mediatek.com1-0/+9
This patch add the connection from RDMA2 to DPI0 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA1 to DSI3stu.hsieh@mediatek.com1-0/+8
This patch add the connection from RDMA1 to DSI3 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA1 to DSI2stu.hsieh@mediatek.com1-0/+9
This patch add the connection from RDMA1 to DSI2 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA1 to DSI1stu.hsieh@mediatek.com1-0/+9
This patch add the connection from RDMA1 to DSI1 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA1 to DPI1stu.hsieh@mediatek.com1-0/+8
This patch add the connection from RDMA1 to DPI1 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA0 to DSI3stu.hsieh@mediatek.com1-0/+4
This patch add the connection from RDMA0 to DSI3 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA0 to DSI2stu.hsieh@mediatek.com1-0/+4
This patch add the connection from RDMA0 to DSI2 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from RDMA0 to DPI0stu.hsieh@mediatek.com1-0/+5
This patch add the connection from RDMA0 to DPI0 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: Update the definition of connection from RDMA1 to DPI0stu.hsieh@mediatek.com1-4/+4
This patch update the definition of connection from RDMA1 to DPI0. Change the term MOUT to SOUT. Because our HW datasheet use the term SOUT to match its function for RDMA. For consistency, changing the name from MOUT to SOUT is better. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add connection from OD1 to RDMA1stu.hsieh@mediatek.com1-0/+4
This patch add the connection from OD1 to RDMA1 for ext path. Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add ddp component OD1stu.hsieh@mediatek.com1-2/+2
This patch add the component OD1 and rename the OD to OD0 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: add ddp component AAL1stu.hsieh@mediatek.com1-1/+1
This patch add component AAL1 and rename AAL to AAL0 Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2018-06-24drm/mediatek: support maximum 64 mutex modstu.hsieh@mediatek.com1-28/+47
This patch support that if modules more than 32, add index more than 31 when using DISP_REG_MUTEX_MOD2 bit Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: add support for Mediatek SoC MT2701yt.shen@mediatek.com1-0/+17
This patch add support for the Mediatek MT2701 DISP subsystem. There is only one OVL engine in MT2701. Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: update display module connectionsyt.shen@mediatek.com1-0/+25
update connections for OVL, RDMA, BLS, DSI Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: add shadow register supportyt.shen@mediatek.com1-0/+25
We need to acquire mutex before using the resources, and need to release it after finished. So we don't need to write registers in the blanking period. Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: add *driver_data for different hardware settingsyt.shen@mediatek.com1-34/+37
There are some hardware settings changed, between MT8173 & MT2701: DISP_OVL address offset changed, color format definition changed. DISP_RDMA fifo size changed. DISP_COLOR offset changed. MIPI_TX pll setting changed. And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod. Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2016-05-06drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.CK Hu1-0/+353
This patch adds an initial DRM driver for the Mediatek MT8173 DISP subsystem. It currently supports two fixed output streams from the OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: YT Shen <yt.shen@mediatek.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: Mao Huang <littlecvr@chromium.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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