aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau/core/engine/fifo (follow)
AgeCommit message (Expand)AuthorFilesLines
2014-06-11drm/nouveau/core: allow event source to handle multiple event types per indexBen Skeggs5-12/+12
2014-06-10drm/nouveau/fifo: add GK20A supportAlexandre Courbot2-0/+36
2014-03-26support for platform devicesAlexandre Courbot1-1/+1
2014-03-26drm/nve0/fifo: bind intrBen Skeggs1-2/+27
2014-03-26drm/nve0/fifo: attempt to recover from engine ctxsw timeoutsBen Skeggs1-0/+44
2014-03-26drm/nve0/fifo: attempt to recover engines from mmu faultsBen Skeggs1-2/+87
2014-03-26drm/nve0/fifo: allow copy engine channel to be looked up by instanceBen Skeggs1-0/+2
2014-03-26drm/nve0/fifo: use runlist event instead of pollingBen Skeggs1-1/+3
2014-03-26drm/nve0/fifo: allow channels to be marked as unrunnableBen Skeggs1-13/+24
2014-03-26drm/nve0/fifo: single printk for sched error dataBen Skeggs1-4/+10
2014-03-26drm/nve0/fifo: single printk for mmu fault dataBen Skeggs1-72/+92
2014-03-26drm/nve0/fifo: ack pb intr individually after handling each unitBen Skeggs1-66/+63
2014-03-26drm/nve0/fifo: runlist intrBen Skeggs1-10/+17
2014-03-26drm/nve0/fifo: engine intrBen Skeggs1-1/+7
2014-03-26drm/nve0/fifo: mask unhandled intr bits when seen, rather than all intrsBen Skeggs1-2/+2
2014-03-26drm/nvc0/fifo: attempt to recover from engine ctxsw timeoutsBen Skeggs1-0/+34
2014-03-26drm/nvc0/fifo: attempt to recover engines from mmu faultsBen Skeggs1-2/+103
2014-03-26drm/nvc0/fifo: use subdev identifiers for bar/ifb fault recovery casesBen Skeggs1-18/+15
2014-03-26drm/nvc0/fifo: use runlist event instead of pollingBen Skeggs1-2/+4
2014-03-26drm/nvc0/fifo: allow channels to be marked as unrunnableBen Skeggs1-10/+22
2014-03-26drm/nvc0/fifo: sched intrBen Skeggs1-2/+22
2014-03-26drm/nvc0/fifo: single printk for mmu fault dataBen Skeggs1-33/+52
2014-03-26drm/nvc0/fifo: ack pb intr individually after handling each unitBen Skeggs1-42/+40
2014-03-26drm/nvc0/fifo: runlist intrBen Skeggs1-14/+32
2014-03-26drm/nvc0/fifo: engine intrBen Skeggs1-12/+40
2014-03-26drm/nvc0/fifo: mask unhandled intr bits when seen, rather than all intrsBen Skeggs1-2/+2
2014-03-26drm/nvc0/fifo: rename a couple of unitsBen Skeggs1-22/+22
2014-03-26drm/nve0/fifo: allocate usermem as neededAlexandre Courbot1-2/+2
2014-02-18drm/nouveau: fix ENG_RUNLIST register addressAlexandre Courbot1-1/+1
2014-01-23drm/nouveau/bar: tidy up the subdev and object class definitionsBen Skeggs2-0/+2
2014-01-23drm/nve0/fifo: recover from mmu faults on bar1/bar3Ben Skeggs1-11/+20
2014-01-23drm/nve0/fifo: keep mmu fault interrupts enabled at all timesBen Skeggs1-1/+16
2014-01-23drm/nve0/fifo: update human-readable mmu fault descriptionsBen Skeggs1-11/+87
2014-01-23drm/nve0/fifo: document more intr status bitsBen Skeggs1-5/+72
2014-01-23drm/nve0/fifo: populate PBDMA status bitfield with more definitionsBen Skeggs1-2/+30
2014-01-23drm/nve0/fifo: s/subfifo/PBDMA/Ben Skeggs1-15/+15
2014-01-23drm/nve0/fifo: s/playlist/runlist/Ben Skeggs1-14/+20
2014-01-23drm/nv108/fifo: initial supportBen Skeggs3-54/+112
2013-12-03drm/nouveau/fifo: Hook up pause and resume for NV50 and NV84+Roy Spliet2-0/+6
2013-11-14drm/nvc0-: remove nasty fifo swmthd hack for flip completion methodBen Skeggs2-14/+0
2013-11-08drm/nouveau/fifo: make external class definitions into pointersBen Skeggs8-16/+16
2013-11-08drm/nouveau/vic: rename PUNK1C1 to PVICBen Skeggs1-3/+3
2013-09-04drm/nouveau/vdec: implement support for VP3 enginesIlia Mirkin1-0/+2
2013-09-04drm/nouveau/core: get rid of math.h, replace log2i with order_base_2Ilia Mirkin4-8/+4
2013-07-05drm/nvf0/fifo: enable supportBen Skeggs1-1/+3
2013-07-01drm/nouveau/bsp/nv84: initial vp2 engine implementationIlia Mirkin1-0/+2
2013-07-01drm/nouveau/vp/nv84: initial vp2 engine implementationIlia Mirkin1-0/+2
2013-07-01drm/nve0/fifo: create our playlists up-front, at startupBen Skeggs1-14/+14
2013-07-01drm/nouveau/fb: initialise vram controller as pfb sub-objectBen Skeggs1-1/+1
2013-07-01drm/nve0/ce: link ce2 to its engine, rather than from graphicsBen Skeggs1-1/+2