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path: root/drivers/pinctrl
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2015-03-25pinctrl: st: Introduce a 'get pin function' callLee Jones1-0/+14
This call fetches the numerical function value a specified pin is currently operating in. Function zero is more often than not the GPIO function. Greater than zero values represent an alternative function. You'd need to either look those up in the Device Tree sources or the Programmer's Manual. Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-19pinctrl: tegra: use signed bitfields for optional fieldsStefan Agner1-20/+20
Optional fields are set to -1 by various preprocessor macros. Make sure the fields can actually store them. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: mt8135/mt8173: Constify of_device_id tableAxel Lin2-10/+6
Also make the table a bit compact. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: mtk-common: Use devm_kcalloc at appropriate placesAxel Lin1-10/+7
Prefer devm_kcalloc over devm_kzalloc with multiply. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: mt8135/mt8173: Fix build error due to missing include fileAxel Lin1-1/+1
Fix below build error: CC drivers/pinctrl/mediatek/pinctrl-mt8135.o In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0: drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error: pinctrl-mtk-common.h: No such file or directory compilation terminated. make[3]: *** [drivers/pinctrl/mediatek/pinctrl-mt8135.o] Error 1 make[2]: *** [drivers/pinctrl/mediatek] Error 2 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: Adjust mt8173 pinctrl kconfigYingjoe Chen1-3/+8
ARM64 maintainer doesn't want to add MACH_* for each SoC. Adjust mt8173 pinctrl kconfig entry so user can manually select it. Also make PINCTRL_MT8135 selectable when COMPILE_TEST is enabled. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: mtk-common: Remove kfreeAxel Lin1-4/+2
Remove erroneous kfree for memory allocated by devm_kzalloc Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: Fix include directiveGuenter Roeck1-1/+1
Fix the following build failure: In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0: drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error: pinctrl-mtk-common.h: No such file or directory seen when building arm:multi_v7_defconfig. Fixes: 94097d89c145 ("pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.") Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: sun4i: GPIOs configured as irq must be set to input before readingHans de Goede3-2/+17
On sun4i-a10, when GPIOs are configured as external interrupt the value for them in the data register does not seem to get updated, so set their mux to input (and restore afterwards) when reading the pin. Missed edges seem to be buffered, so this does not introduce a race condition. I've also tested this on sun5i-a13 and sun7i-a20 and those do not seem to be affected, the input value representation in the data register does seem to correctly get updated to the actual pin value while in irq mode there. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: sh-pfc: Remove r8a7790 platform_device_id entryGeert Uytterhoeven1-3/+0
The r8a7790 platform is now DT-only, the driver doesn't need to match platform devices by name anymore. Remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: sh-pfc: Remove emev2 platform_device_id entryGeert Uytterhoeven1-3/+0
The emev2 platform is now DT-only, the driver doesn't need to match platform devices by name anymore. Remove the corresponding platform_device_id entry. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: sh-pfc: Use u32 to store register addressesGeert Uytterhoeven3-10/+14
Currently all PFC registers lie in low 32-bit address space. Hence use u32 instead of unsigned long to store PFC register addresses in pinctrl tables. All calculations of virtual addresses use a phys_addr_t intermediate, so we know where to add an offset if the 32-bit assumption ever becomes false. While this doesn't impact 32-bit builds, it would save ca. 7 KiB on a 64-bit shmobile_defconfig kernel. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: sh-pfc: Use reg_width instead of reg as sentinelGeert Uytterhoeven1-1/+1
All other loops over sh_pfc_soc_info.data_regs[] use pinmux_data_reg.regwidth as the sentinel, which is safer as zero is never a valid regwidth value (reg could be zero if we start using it to store an offset). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: sh-pfc: Use unsigned int for register/field widths and offsetsGeert Uytterhoeven3-34/+33
As register and field widths and offsets are in the range 1..32, use unsigned int (mostly replacing unsigned long) to store them in local variables and for passing them around. Move to one variable per line, move variables to the beginning of the block where they are used, and drop superfluous initializations while we are at it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: sh-pfc: Store register/field widths in u8 instead of unsigned longGeert Uytterhoeven2-5/+7
Register and field widths are in the range 1..32. Storing them in the pinctrl data in (arrays of) unsigned long wastes space. This decreases the size of a (32-bit) shmobile_defconfig kernel supporting 7 SoCs by 26460 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: add AMD GPIO driver support.Ken Xue4-0/+1147
KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM. Current driver patch only support GPIO in x86. Signed-off-by: Ken Xue <Ken.Xue@amd.com> [Moved back to <linux/gpio.h> header] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: exynos: Remove eint_gpio_init call-back for exynos7 alive pinctrl blockAbhilash Kesavan1-1/+0
The alive pin controller on exynos7 does not support external gpio interrupts. Hence, remove the eint_gpio_init call-back for it. This fixes the following error message seen during exynos7 boot-up: "samsung-pinctrl 10580000.pinctrl: irq number not available" Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: cygnus: add gpio/pinconf driverRay Jui3-0/+930
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO controller, the chipCommonG GPIO controller, and the always-on GPIO controller. Basic PINCONF configurations such as bias pull up/down, and drive strength are also supported in this driver. Pins from the ASIU GPIO controller can be individually muxed to GPIO function, through interaction with the Cygnus IOMUX controller Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Tested-by: Dmitry Torokhov <dtor@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: fix build errorHongzhou Yang1-2/+3
Due to pinconf_generic_parse_dt_config() API changes in pinctrl devel branch, add one parameter to fix build error. Also fix warning: drivers/pinctrl/mediatek/pinctrl-mtk-common.c:718:3: warning: too many arguments for format [-Wformat-extra-args] dev_err(&pdev->dev, "only support pins-are-numbered format\n", ret); ^ by removing extra parameter when calling dev_err in mtk_pctrl_init. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: emulate GPIO interrupt on both-edgesYingjoe Chen4-3/+83
MTK EINT does not support generating interrupt on both edges. Emulate this by changing edge polarity while enable irq, set types and interrupt handling. This follows an example of drivers/gpio/gpio-mxc.c. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18arm64: mediatek: Add Pinctrl/GPIO/EINT driver for mt8173.Hongzhou Yang6-0/+1704
Add mt8173 support using mediatek common pinctrl driver. MT8173 have a different ies_smt setting register than mt8135, so adding this support to common code. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: Add EINT support to MTK pinctrl driver.Maoguang Meng3-2/+435
MTK SoC support external interrupt(EINT) from most SoC pins. Add EINT support to pinctrl driver. Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com> Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.Hongzhou Yang8-0/+3470
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs. The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control. This driver include common driver and mt8135 part. The common driver include the pinctrl driver and GPIO driver. The mt8135 part contain its special device data. Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: sh-pfc: Use u32 to store register dataGeert Uytterhoeven3-22/+21
As PFC registers are either 8, 16, or 32 bits wide, use u32 (mostly replacing unsigned long) to store (parts of) register values and masks. Switch the shadow register operations from {set,clear}_bit() to plain C bit operations, as the former can operate on long data only. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: cygnus: add initial IOMUX driver supportRay Jui3-2/+1038
This adds the initial driver support for the Broadcom Cygnus IOMUX controller. The Cygnus IOMUX controller supports group based mux configuration but allows certain pins to be muxed to GPIO individually Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Tested-by: Dmitry Torokhov <dtor@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: bcm: consolidate Broadcom pinctrl driversRay Jui6-22/+29
Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/* Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: imx: do not implicitly set pin regs to -1Stefan Agner1-2/+6
Commit 3dac1918a491 ("pinctrl: imx: detect uninitialized pins") needs the values in struct imx_pin_reg to be -1. This has been done in a rather unorthodox way by setting the memory to 0xff using memset... Use a proper for loop to initialize the whole array with -1. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18pinctrl: at91: move lock/unlock_as_irq calls into request/releaseBoris Brezillon1-10/+7
The gpiochip_lock_as_irq call can fail and return an error, while the irq_startup is not expected to fail (returns an unsigned int which is not checked by irq core code). irq_request/release_resources functions have been created to address this problem. Move gpiochip_lock/unlock_as_irq calls into irq_request/release_resources functions to prevent using a gpio as an irq if the gpiochip_lock_as_irq call failed. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-10pinctrl: update direction_output function of cherryview driverqipeng.zha1-0/+1
From the comments of gpiod_direction_output(), need to set @value as initial output, so update the lowlevel routine to make it work. Signed-off-by: jason.cj.chen<jason.cj.chen@intel.com> Signed-off-by: qipeng.zha <qipeng.zha@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: qcom: handle input-enable pinconf propertyStanimir Varbanov1-0/+11
This enables support of 'input-enable' pinconf generic property in the pinctrl driver. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: qcom: enable generic pinconfStanimir Varbanov1-4/+2
This makes the pinctrl driver to use the generic pinconf interface. Mainly it gives us a way to use debugfs to dump group configurations. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: at91: simplify probe error handlingBaruch Siach1-5/+1
There is no code ender the 'err' label. Just return the error code directly. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: sirf: fix typo in kernel warning on a bad interruptColin Ian King1-1/+1
Fix typo, "flaged" -> "flagged" Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: tegra: add a driver for Tegra210Stephen Warren3-0/+1593
Tegra210's pinmux supports a different set of pins/options than earlier SoCs, so requires its own driver (well, table of pin-specific data). Cc: devicetree@vger.kernel.org Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: tegra: support nvidia,io-hv DT propertyStephen Warren1-0/+1
Both nvidia,io-hv and nvidia,rcv-sel represent the fact that a particular pin's IO buffers are configured to accept "high voltage" input signals. The TRM for different chips names the register field rcv-sel on older SoCs and io_hv on newer SoCs. Add the new naming option into the pinctrl driver so that DT files can use naming consistent with the TRM. This new property name will be documented in the patch that adds support for the new SoC. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: tegra: some bits move between registersStephen Warren6-6/+36
Some of the pinmux configuration bits that exist in "drive group" registers in Tegra30..Tegra124 move to the "pinmux" registers on future chips. Add a flag to support this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: tegra: driver layout/consistency fixesStephen Warren3-81/+75
Various non-semantic tweaks and layout/consistency fixes for existing Tegra pinctrl drivers. Move the definition of DRV_PINGROUP_REG() before the definition of PINGROUP() so that a future SoC driver can invoke the former from the latter. PINGROUP_BIT_Y(n) is just n, so replace it with n. Re-wrap the parameters to *PINGROUP(). Keep various enums sorted in the Tegra124 driver. Various white-space consistency fixes. These changes aim to update existing drivers to be consistent with future SoC drivers. While we could ignore these tweaks to the existing drivers, I'd like to keep everything as consistent as possible for easy comparison. Besides, I auto-generate the drivers, and maintaining special-cases to keep the differences in place is annoying. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: lantiq: fix include guard #endif commentBaruch Siach1-1/+1
Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: freescale: make of_device_id array constSanjeev Sharma1-1/+1
Make of_device_id array const. Signed-off-by: Sanjeev Sharma <Sanjeev_Sharma@mentor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: sh-pfc: Do not overwrite bias configurationGeert Uytterhoeven1-12/+13
After the last user of the in_pd/in_pu bias parameters of the _PCRH() macro was removed in commit 80da8e02d22caaef ("sh-pfc: r8a7740: Add bias (pull-up/down) pinconf support"), bias parameters are supposed to be configured using the generic pinctl mechanism, which calls the .set_bias() method. However, the PORTCR() macro still represents the control register as consisting of two 4-bit fields. Hence the bias configuration in the uppermost 2 bits is always overwritten with zeroes when a pin is configured for GPIO, disabling any previously configured bias. Use the variable config register macro instead, to represent the register as having 4 fields, and to make sure only the input/output control and function fields are touched. This affects R-Mobile APE6 (r8a73a4), R-Mobile A1 (r8a7740), SH-Mobile AP4 (sh7372), and SH-Mobile AG5 (sh73a0). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: sh-pfc: Remove r8a7791 platform_device_id entryLaurent Pinchart1-3/+0
The r8a7791 platform is now DT-only, the driver doesn't need to match platform devices by name anymore. Remove the corresponding platform_device_id entry. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-06treewide: Fix typo in printk messagesMasanari Iida1-1/+1
This patch fix spelling typo in printk messages. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2015-03-06pinctrl: baytrail: Save pin context over system sleepMika Westerberg1-2/+81
The BIOS might reconfigure pins as it needs when S3 is entered. This might cause drivers using the GPIOs to fail because the state was wrong or interrupts stopped working. Fix this by saving and restoring enough pin context over system sleep. Reported-by: Hans Holmberg <hans.holmberg@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-06pinctrl: baytrail: Rework interrupt handlingMika Westerberg1-44/+56
Instead of handling everything in the driver's first level interrupt handler, we can take advantage of already existing flow handlers that are provided by the IRQ core. This changes the functionality a bit also. Previously the driver looped over pending interrupts in a single loop, restarting the loop if some interrupt changed state. This caused problem with Lenovo Thinkpad 10 digitizer that it was not able to deassert the interrupt before the driver disabled the interrupt for good (looplimit was exhausted). Rework the interrupt handling logic a bit so that we provide proper mask, ack and unmask operations in terms of Baytrail GPIO hardware and loop over pending interrupts only once. If the interrupt remains asserted the first level handler will be re-triggered automatically. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-06pinctrl: baytrail: Clear interrupt triggering from pins that are in GPIO modeMika Westerberg1-7/+29
If the pin is already configured as GPIO and it has any of the triggering flags set, we may get spurious interrupts depending on the state of the pin. Prevent this by clearing the triggering flags on such pins. However, if the pin is also configured as "direct IRQ" we leave the flags as is. Otherwise it will prevent interrupts that are routed directly to IO-APIC. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-06pinctrl: baytrail: Relax GPIO request rulesMika Westerberg1-13/+22
Zotac ZBOX PI320, a Baytrail based mini-PC, has power button connected to a GPIO pin and it is exposed to the operating system as Windows 8 button array. This is implemented in Linux as a driver using gpio_keys. However, BIOS on this particula machine forgot to mux the pin to be a GPIO instead of native function, which results following message to be seen on the console: byt_gpio INT33FC:02: pin 16 cannot be used as GPIO. This causes power button to not work as the driver was not able to request the GPIO it needs. So instead of completely preventing this we allow turning the pin as GPIO but issue warning that something might be wrong. Reported-by: Benjamin Adler <benadler@gmx.net> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-05pinctrl: exynos: Add support for Exynos5433Chanwoo Choi3-0/+156
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi- functional input/output port pins and 135 memory port pins. There are 41 general port groups and 2 memory port groups. Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-04pinctrl: mvebu: add pinctrl driver for Marvell Armada 39xThomas Petazzoni3-0/+437
This commit adds a new pinctrl driver for the Marvell Armada 39x family of processors, which hooks into the existing infrastructure to support pin-muxing on Marvell EBU processors. Two variants of the Armada 39x are supported: 88F6920 (Armada 390) and 88F6928 (Armada 398), which have a few differences in the available functions for certain pins. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-02-11Merge tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlLinus Torvalds44-3135/+7335
Pull pincontrol updates from Linus Walleij: :This is the bulk of pin control changes for the v3.20 cycle: Framework changes and enhancements: - Passing -DDEBUG recursively to subdir drivers so we get debug messages properly turned on. - Infer map type from DT property in the groups parsing code in the generic pinconfig code. - Support for custom parameter passing in generic pin config. This is used when you are using the generic pin config, but want to add a few custom properties that no other driver will use. New drivers: - Driver for the Xilinx Zynq - Driver for the AmLogic Meson SoCs New features in drivers: - Sleep support (suspend/resume) for the Cherryview driver - mvebeu a38x can now mux a UART on pins MPP19 and MPP20 - Migrated the qualcomm driver to generic pin config handling of extended config options in the core code. - Support BUS1 and AUDIO in the Exynos pin controller. - Add some missing functions in the sun6i driver. - Add support for the A31S variant in the sun6i driver. - EMEv2 support in the Renesas PFC driver. - Add support for Qualcomm MSM8916 in the qcom driver. Deleted features - Drop support for the SiRF Marco that was never released to the market. - Drop SH7372 support as the support for this platform is removed from the kernel" * tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (40 commits) sh-pfc: emev2 - Fix mangled author name pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs pinctrl: imx25: fix numbering for pins pinctrl: pinctrl-imx: don't use invalid value of conf_reg pinctrl: qcom: delete pin_config_get/set pinconf operations pinctrl: qcom: Add msm8916 pinctrl driver DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding pinctrl: qcom: increase variable size for register offsets pinctrl: hide PCONFDUMP in #ifdef pinctrl: rockchip: Only mask interrupts; never disable pinctrl: zynq: Fix usb0 pins pinctrl: sh-pfc: sh7372: Remove DT binding documentation pinctrl: sh-pfc: sh7372: Remove PFC support sh-pfc: Add emev2 pinmux support sh-pfc: add macro to define pinmux without function pinctrl: add driver for Amlogic Meson SoCs staging: drivers: pinctrl: Fixed checkpatch.pl warnings pinctrl: exynos: Add AUDIO pin controller for exynos7 sh-pfc: r8a7790: add MLB+ pin group sh-pfc: r8a7791: add MLB+ pin group ...
2015-02-05sh-pfc: emev2 - Fix mangled author nameGeert Uytterhoeven1-1/+1
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Fixes: 1e7d5d849cf4f0c5 ("sh-pfc: Add emev2 pinmux support") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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