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2022-08-01Merge tag 'spi-nor/for-5.20' into mtd/nextRichard Weinberger1-2/+2
SPI NOR core changes: - move SECT_4K_PMC flag out of the core as it's a vendor specific flag - s/addr_width/addr_nbytes: address width means the number of IO lines used for the address, whereas in the code it is used as the number of address bytes. - do not change nor->addr_nbytes at SFDP parsing time. At the SFDP parsing time we should not change members of struct spi_nor, but instead fill members of struct spi_nor_flash_parameters which could later on be used by the callers. - track flash's internal address mode so that we can use 4B opcodes together with opcodes that don't have a 4B opcode correspondent. SPI NOR manufacturer drivers changes: - esmt: Rename "f25l32qa" flash name to "f25l32qa-2s". - micron-st: Skip FSR reading if SPI controller does not support it to allow flashes that support FSR to work even when attached to such SPI controllers. - spansion: Add s25hl-t/s25hs-t IDs and fixups.
2022-08-01Merge remote-tracking branch 'korg_git/nand/next' into mtd/nextRichard Weinberger1-0/+1
2022-07-28mtd: spi-nor: s/addr_width/addr_nbytesTudor Ambarus1-2/+2
Address width was an unfortunate name, as it means the number of IO lines used for the address, whereas in the code it is used as the number of address bytes. s/addr_width/addr_nbytes throughout the entire SPI NOR framework. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220725092505.446315-2-tudor.ambarus@microchip.com
2022-06-09mtd: hyperbus: Make hyperbus_unregister_device() return voidUwe Kleine-König1-3/+1
The only thing that could theoretically fail in that function is mtd_device_unregister(). However it's not supposed to fail and when used correctly it doesn't. So wail loudly if it does anyhow. This matches how other drivers (e.g. nand/raw/nandsim.c) use mtd_device_unregister(). This is a preparation for making platform remove callbacks return void. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220603210758.148493-2-u.kleine-koenig@pengutronix.de
2022-06-06mtd: spinand: Add support for ATO25D1GAAidan MacDonald1-0/+1
Add support for the ATO25D1GA SPI NAND flash. Datasheet: - https://atta.szlcsc.com/upload/public/pdf/source/20191212/C469320_04599D67B03B078044EB65FF5AEDDDE9.pdf Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220604113250.4745-1-aidanmacdonald.0x0@gmail.com
2022-05-24Merge tag 'mtd/for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linuxLinus Torvalds4-2/+51
Pull mtd updates from Miquel Raynal: "MTD core changes: - Call of_platform_populate() for MTD partitions - Check devicetree alias for index - mtdoops: - Add a timestamp to the mtdoops header. - Create a header structure for the saved mtdoops. - Fix the size of the header read buffer. - mtdblock: Warn if opened on NAND - Bindings: - reserved-memory: Support MTD/block device - jedec,spi-nor: remove unneeded properties - Extend fixed-partitions binding - Add Sercomm (Suzhou) Corporation vendor prefix MTD driver changes: - st_spi_fsm: add missing clk_disable_unprepare() in stfsm_remove() - phram: - Allow cached mappings - Allow probing via reserved-memory - maps: ixp4xx: Drop driver - bcm47xxpart: Print correct offset on read error CFI driver changes: - Rename chip_ready variables - Add S29GL064N ID definition - Use chip_ready() for write on S29GL064N - Move and rename chip_check/chip_ready/chip_good_for_write NAND core changes: - Print offset instead of page number for bad blocks Raw NAND controller drivers: - Cadence: Fix possible null-ptr-deref in cadence_nand_dt_probe() - CS553X: simplify the return expression of cs553x_write_ctrl_byte() - Davinci: Remove redundant unsigned comparison to zero - Denali: Use managed device resources - GPMI: - Add large oob bch setting support - Rename the variable ecc_chunk_size - Uninline the gpmi_check_ecc function - Add strict ecc strength check - Refactor BCH geometry settings function - Intel: Fix possible null-ptr-deref in ebu_nand_probe() - MPC5121: Check before clk_disable_unprepare() not needed - Mtk: - MTD_NAND_ECC_MEDIATEK should depend on ARCH_MEDIATEK - Also parse the default nand-ecc-engine property if available - Make mtk_ecc.c a separated module - OMAP ELM: - Convert the bindings to yaml - Describe the bindings for AM64 ELM - Add support for its compatible - Renesas: Use runtime PM instead of the raw clock API and update the bindings accordingly - Rockchip: Check before clk_disable_unprepare() not needed - TMIO: Check return value after calling platform_get_resource() Raw NAND chip driver: - Kioxia: Add support for TH58NVG3S0HBAI4 and TC58NVG0S3HTA00 SPI-NAND chip drivers: - Gigadevice: - Add support for: - GD5FxGM7xExxG - GD5F{2,4}GQ5xExxG - GD5F1GQ5RExxG - GD5FxGQ4xExxG - Fix Quad IO for GD5F1GQ5UExxG - XTX: Add support for XT26G0xA SPI NOR core changes: - Read back written SR value to make sure the write was done correctly. - Introduce a common function for Read ID that manufacturer drivers can use to verify the Octal DTR switch worked correctly. - Add helpers for read/write any register commands so manufacturer drivers don't open code it every time. - Clarify rdsr dummy cycles documentation. - Add debugfs entry to expose internal flash parameters and state. SPI NOR manufacturer drivers changes: - Add support for Winbond W25Q512NW-IM, and Eon EN25QH256A. - Move spi_nor_write_ear() to Winbond module since only Winbond flashes use it. - Rework Micron and Cypress Octal DTR enable methods to improve readability. - Use the common Read ID function to verify switch to Octal DTR mode for Micron and Cypress flashes. - Skip polling status on volatile register writes for Micron and Cypress flashes since the operation is instant" * tag 'mtd/for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (68 commits) mtd: st_spi_fsm: add missing clk_disable_unprepare() in stfsm_remove() dt-bindings: mtd: partitions: Extend fixed-partitions binding dt-bindings: Add Sercomm (Suzhou) Corporation vendor prefix mtd: phram: Allow cached mappings mtd: call of_platform_populate() for MTD partitions mtd: rawnand: renesas: Use runtime PM instead of the raw clock API dt-bindings: mtd: renesas: Fix the NAND controller description mtd: rawnand: mpc5121: Check before clk_disable_unprepare() not needed mtd: rawnand: rockchip: Check before clk_disable_unprepare() not needed mtd: nand: MTD_NAND_ECC_MEDIATEK should depend on ARCH_MEDIATEK mtd: rawnand: cs553x: simplify the return expression of cs553x_write_ctrl_byte() mtd: rawnand: kioxia: Add support for TH58NVG3S0HBAI4 mtd: spi-nor: debugfs: fix format specifier mtd: spi-nor: support eon en25qh256a variant mtd: spi-nor: winbond: add support for W25Q512NW-IM mtd: spi-nor: expose internal parameters via debugfs mtd: spi-nor: export spi_nor_hwcaps_pp2cmd() mtd: spi-nor: move spi_nor_write_ear() to winbond module mtd: spi-nor: amend the rdsr dummy cycles documentation mtd: cfi_cmdset_0002: Rename chip_ready variables ...
2022-05-20Merge tag 'nand/for-5.19' into mtd/nextMiquel Raynal2-0/+48
NAND core: * Print offset instead of page number for bad blocks Raw NAND controller drivers: * Cadence: Fix possible null-ptr-deref in cadence_nand_dt_probe() * CS553X: simplify the return expression of cs553x_write_ctrl_byte() * Davinci: Remove redundant unsigned comparison to zero * Denali: Use managed device resources * GPMI: - Add large oob bch setting support - Rename the variable ecc_chunk_size - Uninline the gpmi_check_ecc function - Add strict ecc strength check - Refactor BCH geometry settings function * Intel: Fix possible null-ptr-deref in ebu_nand_probe() * MPC5121: Check before clk_disable_unprepare() not needed * Mtk: - MTD_NAND_ECC_MEDIATEK should depend on ARCH_MEDIATEK - Also parse the default nand-ecc-engine property if available - Make mtk_ecc.c a separated module * OMAP ELM: - Convert the bindings to yaml - Describe the bindings for AM64 ELM - Add support for its compatible * Renesas: Use runtime PM instead of the raw clock API and update the bindings accordingly * Rockchip: Check before clk_disable_unprepare() not needed * TMIO: Check return value after calling platform_get_resource() Raw NAND chip driver: * Kioxia: Add support for TH58NVG3S0HBAI4 and TC58NVG0S3HTA00 SPI-NAND chip drivers: * Gigadevice: - Add support for: - GD5FxGM7xExxG - GD5F{2,4}GQ5xExxG - GD5F1GQ5RExxG - GD5FxGQ4xExxG - Fix Quad IO for GD5F1GQ5UExxG * XTX: Add support for XT26G0xA Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2022-05-20Merge tag 'spi-nor/for-5.19' into mtd/nextMiquel Raynal1-2/+2
SPI NOR core changes: - Read back written SR value to make sure the write was done correctly. - Introduce a common function for Read ID that manufacturer drivers can use to verify the Octal DTR switch worked correctly. - Add helpers for read/write any register commands so manufacturer drivers don't open code it every time. - Clarify rdsr dummy cycles documentation. - Add debugfs entry to expose internal flash parameters and state. SPI NOR manufacturer drivers changes: - Add support for Winbond W25Q512NW-IM, and Eon EN25QH256A. - Move spi_nor_write_ear() to Winbond module since only Winbond flashes use it. - Rework Micron and Cypress Octal DTR enable methods to improve readability. - Use the common Read ID function to verify switch to Octal DTR mode for Micron and Cypress flashes. - Skip polling status on volatile register writes for Micron and Cypress flashes since the operation is instant. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2022-05-09mtd: spi-nor: expose internal parameters via debugfsMichael Walle1-0/+2
There is no way to gather all information to verify support for a new flash chip. Also if you want to convert an existing flash chip to the new SFDP parsing, there is not enough information to determine if the flash will work like before. To ease this development, expose internal parameters via the debugfs. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220429102018.2361038-2-michael@walle.cc
2022-05-02mtd: spi-nor: move spi_nor_write_ear() to winbond moduleMichael Walle1-2/+0
The "Extended Address Register" is winbond specific. If the flash is larger than 16MiB and is used in 3 byte address mode, it is used to set the remaining address bits. Move the write_ear() function, the opcode macros and the spimem op template into the winbond module and rename them accordingly. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220429100153.2338501-1-michael@walle.cc
2022-04-28mtd: cfi_cmdset_0002: Use chip_ready() for write on S29GL064NTokunori Ikegami1-0/+1
Since commit dfeae1073583("mtd: cfi_cmdset_0002: Change write buffer to check correct value") buffered writes fail on S29GL064N. This is because, on S29GL064N, reads return 0xFF at the end of DQ polling for write completion, where as, chip_good() check expects actual data written to the last location to be returned post DQ polling completion. Fix is to revert to using chip_good() for S29GL064N which only checks for DQ lines to settle down to determine write completion. Link: https://lore.kernel.org/r/b687c259-6413-26c9-d4c9-b3afa69ea124@pengutronix.de/ Fixes: dfeae1073583("mtd: cfi_cmdset_0002: Change write buffer to check correct value") Cc: stable@vger.kernel.org Signed-off-by: Tokunori Ikegami <ikegami.t@gmail.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220323170458.5608-3-ikegami.t@gmail.com
2022-04-27Merge tag 'mtd/mtk-spi-nand-for-5.19' into nand/nextMiquel Raynal1-0/+47
Mediatek ECC changes: * Also parse the default nand-ecc-engine property if available * Make mtk_ecc.c a separated module Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2022-04-27mtd: nand: make mtk_ecc.c a separated moduleChuanhong Guo1-0/+47
this code will be used in mediatek snfi spi-mem controller with pipelined ECC engine. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220424032527.673605-2-gch981213@gmail.com
2022-04-21mtd: spinand: Add support for XTX XT26G0xAFelix Matouschek1-0/+1
Add support for XTX Technology XT26G01AXXXXX, XTX26G02AXXXXX and XTX26G04AXXXXX SPI NAND. These are 3V, 1G/2G/4Gbit serial SLC NAND flash devices with on-die ECC (8bit strength per 512bytes). Tested on Teltonika RUTX10 flashed with OpenWrt. Links: - http://www.xtxtech.com/download/?AId=225 - https://datasheet.lcsc.com/szlcsc/2005251034_XTX-XT26G01AWSEGA_C558841.pdf Signed-off-by: Felix Matouschek <felix@matouschek.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220418132803.664103-1-felix@matouschek.org
2022-04-21mtd: fix 'part' field data corruption in mtd_infoOleksandr Ocheretnyi1-4/+2
Commit 46b5889cc2c5 ("mtd: implement proper partition handling") started using "mtd_get_master_ofs()" in mtd callbacks to determine memory offsets by means of 'part' field from mtd_info, what previously was smashed accessing 'master' field in the mtd_set_dev_defaults() method. That provides wrong offset what causes hardware access errors. Just make 'part', 'master' as separate fields, rather than using union type to avoid 'part' data corruption when mtd_set_dev_defaults() is called. Fixes: 46b5889cc2c5 ("mtd: implement proper partition handling") Signed-off-by: Oleksandr Ocheretnyi <oocheret@cisco.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220417184649.449289-1-oocheret@cisco.com
2022-03-23Merge tag 'nand/for-5.18' into mtd/nextMiquel Raynal1-0/+2
Raw NAND core changes: * Rework of_get_nand_bus_width() * Remove of_get_nand_on_flash_bbt() wrapper * Protect access to rawnand devices while in suspend * bindings: Document the wp-gpios property Rax NAND controller driver changes: * atmel: Fix refcount issue in atmel_nand_controller_init * nandsim: - Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern - Merge repeat codes in ns_switch_state - Replace overflow check with kzalloc to single kcalloc * rockchip: Fix platform_get_irq.cocci warning * stm32_fmc2: Add NAND Write Protect support * pl353: Set the nand chip node as the flash node * brcmnand: Fix sparse warnings in bcma_nand * omap_elm: Remove redundant variable 'errors' * gpmi: - Support fast edo timings for mx28 - Validate controller clock rate - Fix controller timings setting * brcmnand: - Add BCMA shim - BCMA controller uses command shift of 0 - Allow platform data instantation - Add platform data structure for BCMA - Allow working without interrupts - Move OF operations out of brcmnand_init_cs() - Avoid pdev in brcmnand_init_cs() - Allow SoC to provide I/O operations - Assign soc as early as possible Onenand changes: * Check for error irq Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2022-03-18Merge tag 'spi-nor/for-5.18' into mtd/nextMiquel Raynal1-18/+0
SPI NOR core changes: - move vendor specific code out of the core into vendor drivers. - unify all function and object names in the vendor modules. - make setup() callback optional to improve readability. - skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash declaration. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2022-03-14mtd: core: Remove partid and partname debugfs filesTudor Ambarus1-3/+0
partid and partname debugfs files were used just by SPI NOR, but they were replaced by sysfs entries. Since these debugfs files are no longer used in mtd, remove dead code. The directory is kept as it is used by nandsim, mtdswap and docg3. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220225144656.634682-1-tudor.ambarus@microchip.com
2022-02-25mtd: spi-nor: move all spansion specifics into spansion.cMichael Walle1-1/+0
The clear status register flags is only available on spansion flashes. Move all the functions around that into the spanion module. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-29-michael@walle.cc
2022-02-25mtd: spi-nor: move all micron-st specifics into micron-st.cMichael Walle1-8/+0
The flag status register is only available on micron flashes. Move all the functions around that into the micron module. This is almost a mechanical move except for the spi_nor_fsr_ready() which now also checks the normal status register. Previously, this was done in spi_nor_ready(). Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-25-michael@walle.cc
2022-02-25mtd: spi-nor: move all xilinx specifics into xilinx.cMichael Walle1-9/+0
Mechanically move all the xilinx functions to its own module. Then register the new flash specific ready() function. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-22-michael@walle.cc
2022-02-18Merge tag 'mtd/spi-mem-ecc-for-5.18' into mtd/nextMiquel Raynal3-0/+100
Topic branch bringing-in changes related to the support of ECC engines that can be used by SPI controllers to manage SPI NANDs as well as possibly by parallel NAND controllers. In particular, it brings support for Macronix ECC engine that can be used with Macronix SPI controller. The changes touch the NAND core, the NAND ECC core, the spi-mem layer, a SPI controller driver and add a new NAND ECC driver, as well as a number of binding updates. Binding changes: * Vendor prefixes: Clarify Macronix prefix * SPI NAND: Convert spi-nand description file to yaml * Raw NAND chip: Create a NAND chip description * Raw NAND controller: - Harmonize the property types - Fix a comment in the examples - Fix the reg property description * Describe Macronix NAND ECC engine * Macronix SPI controller: - Document the nand-ecc-engine property - Convert to yaml - The interrupt property is not mandatory NAND core changes: * ECC: - Add infrastructure to support hardware engines - Add a new helper to retrieve the ECC context - Provide a helper to retrieve a pilelined engine device NAND-ECC changes: * Macronix ECC engine: - Add Macronix external ECC engine support - Support SPI pipelined mode SPI-NAND core changes: * Delay a little bit the dirmap creation * Create direct mapping descriptors for ECC operations SPI-NAND driver changes: * macronix: Use random program load SPI changes: * Macronix SPI controller: - Fix the transmit path - Create a helper to configure the controller before an operation - Create a helper to ease the start of an operation - Add support for direct mapping - Add support for pipelined ECC operations * spi-mem: - Introduce a capability structure - Check the controller extra capabilities - cadence-quadspi/mxic: Provide capability structures - Kill the spi_mem_dtr_supports_op() helper - Add an ecc parameter to the spi_mem_op structure
2022-02-10spi: mxic: Add support for pipelined ECC operationsMiquel Raynal2-1/+16
Some SPI-NAND chips do not have a proper on-die ECC engine providing error correction/detection. This is particularly an issue on embedded devices with limited resources because all the computations must happen in software, unless an external hardware engine is provided. These external engines are new and can be of two categories: external or pipelined. Macronix is providing both, the former being already supported. The second, however, is very SoC implementation dependent and must be instantiated by the SPI host controller directly. An entire subsystem has been contributed to support these engines which makes the insertion into another subsystem such as SPI quite straightforward without the need for a lot of specific functions. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/linux-mtd/20220202144536.393792-1-miquel.raynal@bootlin.com
2022-02-10mtd: spinand: Create direct mapping descriptors for ECC operationsMiquel Raynal1-0/+2
In order for pipelined ECC engines to be able to enable/disable the ECC engine only when needed and avoid races when future parallel-operations will be supported, we need to provide the information about the use of the ECC engine in the direct mapping hooks. As direct mapping configurations are meant to be static, it is best to create two new mappings: one for regular 'raw' accesses and one for accesses involving correction. It is up to the driver to use or not the new ECC enable boolean contained in the spi-mem operation. As dirmaps are not free (they consume a few pages of MMIO address space) and because these extra entries are only meant to be used by pipelined engines, let's limit their use to this specific type of engine and save a bit of memory with all the other setups. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com
2022-02-10mtd: nand: mxic-ecc: Support SPI pipelined modeMiquel Raynal1-0/+49
Introduce the support for another possible configuration: the ECC engine may work as DMA master (pipelined) and move itself the data to/from the NAND chip into the buffer, applying the necessary corrections/computations on the fly. This driver offers an ECC engine implementation that must be instatiated from a SPI controller driver. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-17-miquel.raynal@bootlin.com
2022-02-09mtd: nand: ecc: Provide a helper to retrieve a pilelined engine deviceMiquel Raynal1-0/+1
In a pipelined engine situation, we might either have the host which internally has support for error correction, or have it using an external hardware block for this purpose. In the former case, the host is also the ECC engine. In the latter case, it is not. In order to get the right pointers on the right devices (for example: in order to devm_* allocate variables), let's introduce this helper which can safely be called by pipelined ECC engines in order to retrieve the right device structure. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@bootlin.com
2022-02-09mtd: rawnand: protect access to rawnand devices while in suspendSean Nyekjaer1-0/+2
Prevent rawnand access while in a suspended state. Commit 013e6292aaf5 ("mtd: rawnand: Simplify the locking") allows the rawnand layer to return errors rather than waiting in a blocking wait. Tested on a iMX6ULL. Fixes: 013e6292aaf5 ("mtd: rawnand: Simplify the locking") Signed-off-by: Sean Nyekjaer <sean@geanix.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220208085213.1838273-1-sean@geanix.com
2022-02-07mtd: Replace the expert mode symbols with a single helperMiquel Raynal1-2/+6
Reduce the number of exported symbols by replacing: - mtd_expert_analysis_warning (the error string) - mtd_expert_analysis_mode (the boolean) with a single helper: - mtd_check_expert_analysis_mode Calling this helper will both check/return the content of the internal boolean -which is not exported anymore- and as well conditionally WARN_ONCE() the user, like it was done before. While on this function, make the error string local to the helper and set it const. Only export this helper when CONFIG_DEBUG_FS is defined to limit the growth of the Linux kernel size only for a debug feature on production kernels. Mechanically update all the consumers. Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220128113414.1121924-1-miquel.raynal@bootlin.com
2022-01-23mtd: nand: Add a new helper to retrieve the ECC contextMiquel Raynal1-0/+5
Introduce nand_to_ecc_ctx() which will allow to easily jump to the private pointer of an ECC context given a NAND device. This is very handy, from the prepare or finish ECC hook, to get the internal context out of the NAND device object. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@bootlin.com
2022-01-23mtd: nand: ecc: Add infrastructure to support hardware enginesMiquel Raynal1-0/+28
Add the necessary helpers to register/unregister hardware ECC engines that will be called from ECC engine drivers. Also add helpers to get the right engine from the user perspective. Keep a reference of the in use ECC engine in order to prevent modules to be unloaded. Put the reference when the engine gets retired. A static list of hardware (only) ECC engines is setup to keep track of the registered engines. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com
2021-12-31Merge tag 'nand/for-5.17' into mtd/nextMiquel Raynal1-0/+2
Raw NAND core: * Export nand_read_page_hwecc_oob_first() GPMC memory controller for OMAP2 NAND controller: * GPMC: - Add support for AM64 SoC and allow build on K3 platforms - Use a compatible match table when checking for NAND controller - Use platform_get_irq() to get the interrupt Raw NAND controller drivers: * OMAP2 NAND controller: - Document the missing 'rb-gpios' DT property - Drop unused variable - Fix force_8bit flag behaviour for DMA mode - Move to exec_op interface - Use platform_get_irq() to get the interrupt * Renesas: - Add new NAND controller driver with its bindings and MAINTAINERS entry * Onenand: - Remove redundant variable ooblen * MPC5121: - Remove unused variable in ads5121_select_chip() * GPMI: - Add ERR007117 protection for nfc_apply_timings - Remove explicit default gpmi clock setting for i.MX6 - Use platform_get_irq_byname() to get the interrupt - Remove unneeded variable * Ingenic: - JZ4740 needs 'oob_first' read page function * Davinci: - Rewrite function description - Avoid duplicated page read - Don't calculate ECC when reading page Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31Merge tag 'spi-nor/for-5.17' into mtd/nextMiquel Raynal1-2/+0
SPI NOR core changes: - Add Pratyush as SPI NOR co-maintainer. - Flash parameters initialization was done in a spaghetti way. Clean flash parameters initialization. - Rework the flash_info flags and clarify where one should be used. - Initialize all flash parameters based on JESD216 SFDP where possible. Flash parameters and settings that are SFDP discoverable should not be duplicated via flash_info flags at flash declaration. - Remove debugfs entries that duplicate sysfs entries. SPI NOR manufacturer drivers changes: - Use late_init() hook in various drivers to make it clear that those flash parameters are either not declared in the JESD216 SFDP standard, or the SFDP tables which define those flash parameters are not defined by the flash. - Fix mtd size for s3an flashes. - Write 2 bytes when disabling Octal DTR mode: 1 byte long transactions are not allowed in 8D-8D-8D mode. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-09mtd: Introduce an expert mode for forensics and debugging purposesMiquel Raynal1-0/+3
When developping NAND controller drivers or when debugging filesystem corruptions, it is quite common to need hacking locally into the MTD/NAND core in order to get access to the content of the bad blocks. Instead of having multiple implementations out there let's provide a simple yet effective specific MTD-wide debugfs entry to fully disable these checks on purpose. A warning is added to inform the user when this mode gets enabled. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211118114659.1282855-1-miquel.raynal@bootlin.com
2021-12-03mtd: remove unused header file <linux/mtd/latch-addr-flash.h>Jonathan Corbet1-29/+0
Commit d24dbd7541ff ("mtd: maps: Get rid of the latch-addr-flash driver") removed the last user of <linux/mtd/latch-addr-flash.h> but left the header file behind. Nothing uses this file, delete it now. Cc: Boris Brezillon <bbrezillon@kernel.org> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: linux-mtd@lists.infradead.org Signed-off-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211102220203.940290-7-corbet@lwn.net
2021-11-19mtd: rawnand: Export nand_read_page_hwecc_oob_first()Paul Cercueil1-0/+2
Move the function nand_read_page_hwecc_oob_first() (previously nand_davinci_read_page_hwecc_oob_first()) to nand_base.c, and export it as a GPL symbol, so that it can be used by more modules. Cc: <stable@vger.kernel.org> # v5.2 Fixes: a0ac778eb82c ("mtd: rawnand: ingenic: Add support for the JZ4740") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211016132228.40254-4-paul@crapouillou.net
2021-11-17mtd: spi-nor: Get rid of nor->page_sizeTudor Ambarus1-2/+0
nor->page_size duplicated what nor->params->page_size indicates for no good reason. page_size is a flash parameter of fixed value and it is better suited to be found in nor->params->page_size. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20211029172633.886453-5-tudor.ambarus@microchip.com
2021-09-14mtd: Remove obsolete macros only used by the old nand_ecclayout structGONG, Ruiqi1-2/+0
All uses of MTD_MAX_{OOBFREE,ECCPOS}_ENTRIES_LARGE have been removed as commit ef5eeea6e911 ("mtd: nand: brcm: switch to mtd_ooblayout_ops") and commit aab616e31d1c ("mtd: kill the nand_ecclayout struct") replaced struct nand_ecclayout by the new mtd_ooblayout_ops interface. Remove these two macros therefore. Reported-by: Yi Yang <yiyang13@huawei.com> Signed-off-by: GONG, Ruiqi <gongruiqi1@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210830083356.31702-1-gongruiqi1@huawei.com
2021-07-05Merge tag 'mtd/for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linuxLinus Torvalds4-19/+187
Pull MTD updates from Richard Weinberger: "MTD core changes: - Convert list_for_each to entry variant - Use MTD_DEVICE_ATTR_RO/RW() helper macros - Remove unnecessary OOM messages - Potential NULL dereference in mtd_otp_size() - Fix freeing of otp_info buffer - Create partname and partid debug files for child MTDs - tests: - Remove redundant assignment to err - Fix error return code in mtd_oobtest_init() - Add OTP NVMEM provider support - Allow specifying of_node - Convert sysfs sprintf/snprintf family to sysfs_emit Bindings changes: - Convert ti,am654-hbmc.txt to YAML schema - spi-nor: add otp property - Add OTP bindings - add YAML schema for the generic MTD bindings - Add brcm,trx-magic MTD device drivers changes: - Add support for microchip 48l640 EERAM - Remove superfluous "break" - sm_ftl: - Fix alignment of block comment - nftl: - Return -ENOMEM when kmalloc failed - nftlcore: - Remove set but rewrite variables - phram: - Fix error return code in phram_setup() - plat-ram: - Remove redundant dev_err call in platram_probe() MTD parsers changes: - Qcom: - Fix leaking of partition name - Redboot: - Fix style issues - Seek fis-index-block in the right node - trx: - Allow to use TRX parser on Mediatek SoCs - Allow to specify brcm, trx-magic in DT Raw NAND core: - Allow SDR timings to be nacked - Bring support for NV-DDR timings which involved a number of small preparation changes to bring new helpers, properly introduce NV-DDR structures, fill them, differenciate them and pick the best timing set. - Add the necessary infrastructure to parse the new gpio-cs property which aims at enlarging the number of available CS when a hardware controller is too constrained. - Update dead URL - Silence static checker warning in nand_setup_interface() - BBT: - Fix corner case in bad block table handling - onfi: - Use more recent ONFI specification wording - Use the BIT() macro when possible Raw NAND controller drivers: - Atmel: - Ensure the data interface is supported. - Arasan: - Finer grain NV-DDR configuration - Rename the data interface register - Use the right DMA mask - Leverage additional GPIO CS - Ensure proper configuration for the asserted target - Add support for the NV-DDR interface - Fix a macro parameter - brcmnand: - Convert bindings to json-schema - OMAP: - Various fixes and style improvements - Add larger page NAND chips support - PL35X: - New driver - QCOM: - Avoid writing to obsolete register - Delete an unneeded bool conversion - Allow override of partition parser - Marvell: - Minor documentation correction - Add missing clk_disable_unprepare() on error in marvell_nfc_resume() - R852: - Use DEVICE_ATTR_RO() helper macro - MTK: - Remove redundant dev_err call in mtk_ecc_probe() - HISI504: - Remove redundant dev_err call in probe SPI-NAND core: - Light reorganisation for the introduction of a core resume handler - Fix double counting of ECC stats SPI-NAND manufacturer drivers: - Macronix: - Add support for serial NAND flash SPI NOR core changes: - Ability to dump SFDP tables via sysfs - Support for erasing OTP regions on Winbond and similar flashes - Few API doc updates and fixes - Locking support for MX25L12805D SPI NOR controller drivers changes: - Use SPI_MODE_X_MASK in nxp-spifi - Intel Alder Lake-M SPI serial flash support" * tag 'mtd/for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (125 commits) mtd: spi-nor: remove redundant continue statement mtd: rawnand: omap: Add larger page NAND chips support mtd: rawnand: omap: Various style fixes mtd: rawnand: omap: Check return values mtd: rawnand: omap: Rename a macro mtd: rawnand: omap: Aggregate the HW configuration of the ELM mtd: rawnand: pl353: Add support for the ARM PL353 SMC NAND controller dt-bindings: mtd: pl353-nand: Describe this hardware controller MAINTAINERS: Add PL353 NAND controller entry mtd: rawnand: qcom: avoid writing to obsolete register mtd: rawnand: marvell: Minor documentation correction mtd: rawnand: r852: use DEVICE_ATTR_RO() helper macro mtd: spinand: add SPI-NAND MTD resume handler mtd: spinand: Add spinand_init_flash() helper mtd: spinand: add spinand_read_cfg() helper mtd: rawnand: marvell: add missing clk_disable_unprepare() on error in marvell_nfc_resume() mtd: rawnand: arasan: Finer grain NV-DDR configuration mtd: rawnand: arasan: Rename the data interface register mtd: rawnand: onfi: Fix endianness when reading NV-DDR values mtd: rawnand: arasan: Use the right DMA mask ...
2021-06-30Merge tag 'spi-nor/for-5.14' into mtd/nextMiquel Raynal1-0/+2
SPI NOR core changes: - Ability to dump SFDP tables via sysfs - Support for erasing OTP regions on Winbond and similar flashes - Few API doc updates and fixes - Locking support for MX25L12805D SPI NOR controller drivers changes: - Use SPI_MODE_X_MASK in nxp-spifi - Intel Alder Lake-M SPI serial flash support
2021-06-29Merge tag 'nand/for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/nextRichard Weinberger2-19/+183
Raw NAND core: * Allow SDR timings to be nacked * Bring support for NV-DDR timings which involved a number of small preparation changes to bring new helpers, properly introduce NV-DDR structures, fill them, differenciate them and pick the best timing set. * Add the necessary infrastructure to parse the new gpio-cs property which aims at enlarging the number of available CS when a hardware controller is too constrained. * Update dead URL * Silence static checker warning in nand_setup_interface() * BBT: - Fix corner case in bad block table handling * onfi: - Use more recent ONFI specification wording - Use the BIT() macro when possible Raw NAND controller drivers: * Atmel: - Ensure the data interface is supported. * Arasan: - Finer grain NV-DDR configuration - Rename the data interface register - Use the right DMA mask - Leverage additional GPIO CS - Ensure proper configuration for the asserted target - Add support for the NV-DDR interface - Fix a macro parameter * brcmnand: - Convert bindings to json-schema * OMAP: - Various fixes and style improvements - Add larger page NAND chips support * PL35X: - New driver * QCOM: - Avoid writing to obsolete register - Delete an unneeded bool conversion - Allow override of partition parser * Marvell: - Minor documentation correction - Add missing clk_disable_unprepare() on error in marvell_nfc_resume() * R852: - Use DEVICE_ATTR_RO() helper macro * MTK: - Remove redundant dev_err call in mtk_ecc_probe() * HISI504: - Remove redundant dev_err call in probe SPI-NAND core: * Light reorganisation for the introduction of a core resume handler * Fix double counting of ECC stats SPI-NAND manufacturer drivers: * Macronix: - Add support for serial NAND flash
2021-06-15mtd: spi-nor: sfdp: save a copy of the SFDP dataMichael Walle1-0/+2
Due to possible mode switching to 8D-8D-8D, it might not be possible to read the SFDP after the initial probe. To be able to dump the SFDP via sysfs afterwards, make a complete copy of it. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-06-03mtd: spinand: use the spi-mem poll status APIsPatrice Chotard1-0/+22
Make use of spi-mem poll status APIs to let advanced controllers optimize wait operations. This should also fix the high CPU usage for system that don't have a dedicated STATUS poll block logic. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20210518162754.15940-3-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-05-26mtd: rawnand: Add a helper to parse the gpio-cs DT propertyMiquel Raynal1-0/+4
New chips may feature a lot of CS because of their extended length. As many controllers have been designed a decade ago, they usually only feature just a couple. This does not mean that the entire range of these chips cannot be accessed: it is just a matter of adding more GPIO CS in the hardware design. A DT property has been added to describe the CS array: cs-gpios. Here is the code parsing it this new property, allocating what needs to be, requesting the GPIOs and returning an array with the additional available CS. The first entries of this array are left empty and are reserved for native CS. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210526093242.183847-3-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Move struct gpio_desc declaration to the topMiquel Raynal1-1/+1
The struct gpio_desc is declared in the middle of the rawnand.h header, right before the first function using it (nand_gpio_waitrdy). Before adding a new function and to make it clear: move the declaration to the top of the file. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210526093242.183847-2-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Support enabling NV-DDR through SET_FEATURESMiquel Raynal1-0/+5
Until now the parameter of the ADDR_TIMING_MODE feature was just the ONFI timing mode (from 0 to 5) because we were only supporting the SDR data interface. In the same byte, bits 4 and 5 indicate which data interface is being configured so use them to set the right mode and also read them back to ensure the right timing has been setup on the chip's side. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-17-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Access SDR and NV-DDR timings through a common macroMiquel Raynal1-0/+28
Most timings related to the bus timings are different between SDR and NV-DDR. However, we identified 9 individual timings which are more related to the NAND chip internals. These are common between the two interface types. Fortunately, only these common timings are being shared through the NAND core and its ->exec_op() interface, which allows the writing of a simple macro checking the interface type and depending on it, returning either the relevant SDR timing or the NV-DDR timing. This is the purpose of the NAND_COMMON_TIMING_PS() macro. As all this is evaluated at build time, one will immediately be notified in case a non common timing is being accessed through this macro. Two handy macros are also inserted at the same time, which use PSEC_TO_NSEC or PSEC_TO_MSEC so that it is very easy to return timings in milli-, nano- or pico-seconds, as usually requested by the internal API. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-14-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Add onfi_fill_nvddr_interface_config() helperMiquel Raynal1-0/+2
Same logic as for the SDR path, let's create a onfi_fill_nvddr_interface_config() helper to fill an interface configuration structure with NV-DDR timings, given a specific ONFI mode. There is one additional thing to do compared to SDR mode: tCAD timing can be fast or slow and this depends on an ONFI parameter page bit. By default the slow value is declared in the timings structure definition, but this helper can shrink it down if necessary. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-12-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Retrieve NV-DDR timing modes from the ONFI parameter pageMiquel Raynal1-0/+3
When parsing the ONFI parameter page, save the available NV-DDR timing modes in the core's dynamic ONFI structure. Once available to the rest of the core out of the ONFI driver, these values will then be used to derive the best timing mode. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-10-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Add NV-DDR timingsMiquel Raynal1-0/+112
Create the relevant ONFI NV-DDR timings structure and fill it with default values from the ONFI specification. Add the relevant structure entries and helpers. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-9-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Clarify the NV-DDR entries in the ONFI structureMiquel Raynal1-2/+3
Both src_sync_timing_mode and src_ssync_features entries of the ONFI parameter page have been updated and now are named nvddr_timing_modes, nvddr2_timing_modes and nvddr_nvddr2_features, which is much more understandable for someone which do not know the history of the ONFI specification. Update the relevant structure with regard to these changes. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-8-miquel.raynal@bootlin.com