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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-12-12 17:27:49 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-12-27 09:45:08 +0100 |
| commit | 5edf5b51e760af749c4a8e67cde92db4f3680be5 (patch) | |
| tree | 4059e547de6a7c87b47689c7df215b24a5e030b7 /scripts/generate_rust_analyzer.py | |
| parent | clk: renesas: r9a09g011: Add TIM clock and reset entries (diff) | |
| download | linux-rng-5edf5b51e760af749c4a8e67cde92db4f3680be5.tar.xz linux-rng-5edf5b51e760af749c4a8e67cde92db4f3680be5.zip | |
clk: renesas: r9a09g011: Add USB clock and reset entries
Add USB clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221212172804.1277751-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions