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author | 2023-10-27 16:52:51 -1000 | |
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committer | 2023-10-27 16:52:51 -1000 | |
commit | 67d4c87945b2d9678347eaa4567d62dd56dc9713 (patch) | |
tree | 53c282767027694f2246e6fc2e28a2cf318baeca /scripts/generate_rust_analyzer.py | |
parent | Merge tag 'pull-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs (diff) | |
parent | clk: stm32: Fix a signedness issue in clk_stm32_composite_determine_rate() (diff) | |
download | linux-rng-67d4c87945b2d9678347eaa4567d62dd56dc9713.tar.xz linux-rng-67d4c87945b2d9678347eaa4567d62dd56dc9713.zip |
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"Three fixes, one for the clk framework and two for clk drivers:
- Avoid an oops in possible_parent_show() by checking for no parent
properly when a DT index based lookup is used
- Handle errors returned from divider_ro_round_rate() in
clk_stm32_composite_determine_rate()
- Fix clk_ops::determine_rate() implementation of socfpga's
gateclk_ops that was ruining uart output because the divider
was forgotten about"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: stm32: Fix a signedness issue in clk_stm32_composite_determine_rate()
clk: Sanitize possible_parent_show to Handle Return Value of of_clk_get_parent_name
clk: socfpga: gate: Account for the divider in determine_rate
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions