diff options
| author |   Siddharth Vadapalli <s-vadapalli@ti.com> | 2023-03-15 11:53:06 +0530 |
|---|---|---|
| committer |   Nishanth Menon <nm@ti.com> | 2023-03-20 15:32:20 -0500 |
| commit | d3bac98015da55866891054a2aeb42af7904fca8 (patch) | |
| tree | b66f962e78d0d847b743b30be88cec7f22cf5850 /scripts/generate_rust_analyzer.py | |
| parent | arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode (diff) | |
| download | linux-rng-d3bac98015da55866891054a2aeb42af7904fca8.tar.xz linux-rng-d3bac98015da55866891054a2aeb42af7904fca8.zip | |
arm64: dts: ti: j7200-main: Add CPSW5G nodes
TI's J7200 SoC has a 5 port Ethernet Switch instance with 4 external
ports and 1 host port, referred to as CPSW5G.
Add device-tree nodes for CPSW5G and disable it by default. Device-tree
overlays will be used to enable it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230315062307.1612220-4-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions