diff options
| author |   Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-08-22 18:27:46 +0300 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-09-02 10:15:31 +0200 |
| commit | f0fe60cae63573c801246204414e70035770bdc6 (patch) | |
| tree | efb46b6eb5454a78510cd7db920ec98ee9e478e7 /scripts/generate_rust_analyzer.py | |
| parent | dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints (diff) | |
| download | linux-rng-f0fe60cae63573c801246204414e70035770bdc6.tar.xz linux-rng-f0fe60cae63573c801246204414e70035770bdc6.zip | |
clk: renesas: r9a08g045: Add clocks, resets and power domains for USB
Add clocks, resets and power domains for USB modules available on the
Renesas RZ/G3S SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240822152801.602318-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions