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* ASoC: meson: axg-fifo: use FIELD helpersJerome Brunet2024-02-271-7/+5
| | | | | | | | Use FIELD_GET() and FIELD_PREP() helpers instead of doing it manually. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://msgid.link/r/20240227150826.573581-1-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: meson: axg-fifo: take continuous ratesJerome Brunet2024-02-261-2/+0
| | | | | | | | | | | | | | | The rate of the stream does not matter for the fifos of the axg family. Fifos will just push or pull data to/from the DDR according to consumption or production of the downstream element, which is the DPCM backend. Drop the rate list and allow continuous rates. The lower and upper rate are set according what is known to work with the different backends This allows the PDM input backend to also use continuous rates. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://msgid.link/r/20240223175116.2005407-6-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: meson: axg: extend TDM maximum sample rate to 384kHzJerome Brunet2023-09-111-1/+1
| | | | | | | | | | | The TDM HW on the axg SoC families and derivatives actually supports 384kHz sampling rate. Update the fifo and tdm interface constraints accordingly. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20230907090910.13546-1-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: meson: axg-fifo: relax period size constraintsJerome Brunet2019-12-181-2/+0
| | | | | | | | | | Now that the fifo depths and thresholds are properly in the axg-fifo driver, we can relax the constraints on period. As long as the period is a multiple of the fifo burst size (8 bytes) things should be OK. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20191218172420.1199117-5-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: meson: axg-fifo: improve depth handlingJerome Brunet2019-12-181-0/+1
| | | | | | | | | | | | | | | Let the fifo driver parse the fifo depth from DT. Eventually all DT should have this property. Until it is actually the case, default to 256 bytes if the property is missing. 256 bytes is the size of the smallest fifo on the supported SoCs. On the supported SoC, fifo A is usually bigger than the other ones. With depth known, we can improve the usage of the fifo and adapt the setup of request threshold. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20191218172420.1199117-4-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: meson: axg-fifo: fix fifo threshold setupJerome Brunet2019-12-181-2/+4
| | | | | | | | | | | | | | | | | | On TODDR sm1, the fifo threshold register field is slightly different compared to the other SoCs. This leads to the fifo A being flushed to memory every 8kB. If the period is smaller than that, several periods are pushed to memory and notified at once. This is not ideal. Fix the register field update. With this, the fifos are flushed every 128B. We could still do better, like adapt the threshold depending on the period size, but at least it consistent across the different SoC/fifos Fixes: 5ac825c3d85e ("ASoC: meson: axg-toddr: add sm1 support") Reported-by: Alden DSouza <aldend@google.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20191218172420.1199117-2-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: meson: remove snd_pcm_opsKuninori Morimoto2019-10-081-3/+17
| | | | | | | | | snd_pcm_ops is no longer needed. Let's use component driver callback. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87muej90e4.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: meson: axg-frddr: add sm1 supportJerome Brunet2019-09-051-0/+1
| | | | | | | | On sm1, the output routing bits have moved to CTRL2 register Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20190905120120.31752-7-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: meson: axg-fifo: add g12a supportJerome Brunet2019-04-051-0/+2
| | | | | | | | | | | | | The g12a fifos gained the ability to set the initial address of the pointer within the buffer, instead of defaulting to the buffer start address. It is not very useful to us (yet) but we need to put a copy the buffer start address in the related register for the fifo to work properly on the g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: meson: axg-toddr: add support for spdifin backendJerome Brunet2018-12-131-1/+2
| | | | | | | | | | | | | | | add IEC958_SUBFRAME_LE to the list of format accepted by the fifo frontend. As opposed to what was initially noted in the toddr dai driver, the spdifin does not place the msb at bit 28, it just output a whole spdif subframe. Placing the msb at bit 28 in the toddr driver just filters out the parity, user, channel status and validity bits. It is better to just provide the whole spdif subframe to the userspace and let the iec958 plugin deal with it. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: meson: add axg fifo base driverJerome Brunet2018-07-181-0/+80
Amlogic's axg SoCs have two types of fifos which are the memory interfaces of the audio subsystem. FRDDR provides the playback interface while TODDR provides the capture interface. The way these fifos operate is very similar. Only a few settings are specific to each. They implement the same pcm driver here and the specifics of each will be dealt with the related DAI driver. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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