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path: root/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
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authorYongqiang Sun <yongqiang.sun@amd.com>2020-10-30 09:29:07 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-11-10 14:26:10 -0500
commit4b0b1d05265b044472a23b76d5fda8d7fb218144 (patch)
tree4daeb9c893028eb5590445f22acf0b4bfc00fb63 /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
parentdrm/amd/display: 3.2.111 (diff)
downloadlinux-4b0b1d05265b044472a23b76d5fda8d7fb218144.tar.xz
linux-4b0b1d05265b044472a23b76d5fda8d7fb218144.zip
drm/amd/display: check actual clock value.
[Why] Actual dpp/disp clock PMFW set are always equal or more than requested. Need to cache the actual clock for debugging purpose. [How] Add actuall dpp/disp clk in clock manager and save it when set clocks. Add an ASSERT in case of actual clock less than requested. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 9a374522e963..ab2b9c61e565 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -136,6 +136,10 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis
}
}
+ // pmfw always set clock more than or equal requested clock
+ if (!IS_DIAG_DC(dc->ctx->dce_environment))
+ ASSERT(actual_dispclk_set_mhz >= requested_dispclk_khz / 1000);
+
return actual_dispclk_set_mhz * 1000;
}
@@ -194,12 +198,16 @@ void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phy
int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
{
int actual_dppclk_set_mhz = -1;
+ struct dc *dc = clk_mgr->base.ctx->dc;
actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDppclkFreq,
requested_dpp_khz / 1000);
+ if (!IS_DIAG_DC(dc->ctx->dce_environment))
+ ASSERT(actual_dppclk_set_mhz >= requested_dpp_khz / 1000);
+
return actual_dppclk_set_mhz * 1000;
}