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| author |   Maxim Mikityanskiy <maximmi@nvidia.com> | 2022-10-01 21:56:23 -0700 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2022-10-03 16:55:28 -0700 |
| commit | 9f123f740428e96ef2eae8b5e2876b675b6a4605 (patch) | |
| tree | 8ceeb449d2110256447840e894b5cb286a5b42fa /drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c | |
| parent | net/mlx5e: xsk: Use umr_mode to calculate striding RQ parameters (diff) | |
| download | linux-9f123f740428e96ef2eae8b5e2876b675b6a4605.tar.xz linux-9f123f740428e96ef2eae8b5e2876b675b6a4605.zip | |
net/mlx5e: Improve MTT/KSM alignment
Make mlx5e_mpwrq_mtts_per_wqe take into account that KSM requires
smaller alignment than MTT.
Ensure that there is always an even amount of MTTs in a UMR WQE, so that
complete octwords are formed, and no garbage is mapped.
Drop extra alignment in MLX5_MTT_OCTW that may cause setting too big
ucseg->xlt_octowords, also leading to mapping garbage.
Generalize some calculations by introducing the MLX5_OCTWORD constant.
Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c index e12a856331b8..4b2df2895505 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c @@ -66,9 +66,10 @@ int mlx5e_xsk_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) umr_wqe->ctrl.opmod_idx_opcode = cpu_to_be32((icosq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | MLX5_OPCODE_UMR); + /* Optimized for speed: keep in sync with mlx5e_mpwrq_umr_entry_size. */ offset = ix * rq->mpwqe.mtts_per_wqe; if (likely(rq->mpwqe.umr_mode == MLX5E_MPWRQ_UMR_MODE_ALIGNED)) - offset = MLX5_ALIGNED_MTTS_OCTW(offset); + offset = offset * sizeof(struct mlx5_mtt) / MLX5_OCTWORD; umr_wqe->uctrl.xlt_offset = cpu_to_be16(offset); icosq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) { |