diff options
| author |   Jiri Pirko <jiri@nvidia.com> | 2020-11-10 11:48:51 +0200 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2020-11-12 15:55:20 -0800 |
| commit | d271cf9f298bedc4114ea4009d9488a3e58f6f82 (patch) | |
| tree | 3f26c7b24c03033298669eec597ec4057481c138 /drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c | |
| parent | mlxsw: spectrum_router: Push out RALUE pack into separate helper (diff) | |
| download | linux-d271cf9f298bedc4114ea4009d9488a3e58f6f82.tar.xz linux-d271cf9f298bedc4114ea4009d9488a3e58f6f82.zip | |
mlxsw: spectrum: Export RALUE pack helper and use it from IPIP
As the RALUE packing is going to be put into op, make the user from
IPIP code use the same helper as the router code does.
Signed-off-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c | 17 |
1 files changed, 2 insertions, 15 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c index f8b9b5be8247..0f0064392468 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c @@ -188,22 +188,9 @@ mlxsw_sp_ipip_fib_entry_op_gre4_ralue(struct mlxsw_sp *mlxsw_sp, u32 tunnel_index) { char *ralue_pl = op_ctx->ralue_pl; - enum mlxsw_reg_ralue_op ralue_op; - - switch (op) { - case MLXSW_SP_FIB_ENTRY_OP_WRITE: - ralue_op = MLXSW_REG_RALUE_OP_WRITE_WRITE; - break; - case MLXSW_SP_FIB_ENTRY_OP_DELETE: - ralue_op = MLXSW_REG_RALUE_OP_WRITE_DELETE; - break; - default: - WARN_ON_ONCE(1); - return -EINVAL; - } - mlxsw_reg_ralue_pack4(ralue_pl, MLXSW_REG_RALXX_PROTOCOL_IPV4, ralue_op, - ul_vr_id, prefix_len, dip); + mlxsw_sp_fib_entry_ralue_pack(ralue_pl, MLXSW_SP_L3_PROTO_IPV4, op, + ul_vr_id, prefix_len, (unsigned char *) &dip); mlxsw_reg_ralue_act_ip2me_tun_pack(ralue_pl, tunnel_index); return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ralue), ralue_pl); } |