diff options
| author |   Shannon Nelson <shannon.nelson@amd.com> | 2023-02-10 16:50:17 -0800 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2023-02-13 11:05:12 +0000 |
| commit | 40bc471dc714036c8ed223f9aa04b1b2072fb9db (patch) | |
| tree | 27035128c9e832e7c420c6fe7fdb7cf57c7dc47b /drivers/net/ethernet/pensando/ionic/ionic_lif.h | |
| parent | net: ethtool: extend ringparam set/get APIs for rx_push (diff) | |
| download | linux-40bc471dc714036c8ed223f9aa04b1b2072fb9db.tar.xz linux-40bc471dc714036c8ed223f9aa04b1b2072fb9db.zip | |
ionic: add tx/rx-push support with device Component Memory Buffers
The ionic device has on-board memory (CMB) that can be used
for descriptors as a way to speed descriptor access for faster
packet processing. It is rumored to improve latency and/or
packets-per-second for some profiles of small packet traffic,
although your mileage may vary.
Signed-off-by: Shannon Nelson <shannon.nelson@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/pensando/ionic/ionic_lif.h')
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_lif.h | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h index 734519895614..c9c4c46d5a16 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h @@ -59,6 +59,7 @@ struct ionic_rx_stats { #define IONIC_QCQ_F_TX_STATS BIT(3) #define IONIC_QCQ_F_RX_STATS BIT(4) #define IONIC_QCQ_F_NOTIFYQ BIT(5) +#define IONIC_QCQ_F_CMB_RINGS BIT(6) struct ionic_qcq { void *q_base; @@ -70,6 +71,11 @@ struct ionic_qcq { void *sg_base; dma_addr_t sg_base_pa; u32 sg_size; + void __iomem *cmb_q_base; + phys_addr_t cmb_q_base_pa; + u32 cmb_q_size; + u32 cmb_pgid; + u32 cmb_order; struct dim dim; struct ionic_queue q; struct ionic_cq cq; @@ -142,6 +148,8 @@ enum ionic_lif_state_flags { IONIC_LIF_F_BROKEN, IONIC_LIF_F_TX_DIM_INTR, IONIC_LIF_F_RX_DIM_INTR, + IONIC_LIF_F_CMB_TX_RINGS, + IONIC_LIF_F_CMB_RX_RINGS, /* leave this as last */ IONIC_LIF_F_STATE_SIZE @@ -245,8 +253,10 @@ struct ionic_queue_params { unsigned int nxqs; unsigned int ntxq_descs; unsigned int nrxq_descs; - unsigned int intr_split; u64 rxq_features; + bool intr_split; + bool cmb_tx; + bool cmb_rx; }; static inline void ionic_init_queue_params(struct ionic_lif *lif, @@ -255,8 +265,34 @@ static inline void ionic_init_queue_params(struct ionic_lif *lif, qparam->nxqs = lif->nxqs; qparam->ntxq_descs = lif->ntxq_descs; qparam->nrxq_descs = lif->nrxq_descs; - qparam->intr_split = test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); qparam->rxq_features = lif->rxq_features; + qparam->intr_split = test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); + qparam->cmb_tx = test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); + qparam->cmb_rx = test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); +} + +static inline void ionic_set_queue_params(struct ionic_lif *lif, + struct ionic_queue_params *qparam) +{ + lif->nxqs = qparam->nxqs; + lif->ntxq_descs = qparam->ntxq_descs; + lif->nrxq_descs = qparam->nrxq_descs; + lif->rxq_features = qparam->rxq_features; + + if (qparam->intr_split) + set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); + else + clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); + + if (qparam->cmb_tx) + set_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); + else + clear_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state); + + if (qparam->cmb_rx) + set_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); + else + clear_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state); } static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs) |