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| author |   Max Filippov <jcmvbkbc@gmail.com> | 2022-04-25 17:16:01 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2022-05-06 15:27:40 -0700 |
| commit | 64407f6a9e0731c11a65119b7372dbe5b3a42eb9 (patch) | |
| tree | 643bcc7b05acf59e3e7a09e92c6c07ac217c38ad /linux-user/syscall.c | |
| parent | tests/tcg/xtensa: restore vecbase SR after test (diff) | |
| download | qemu-64407f6a9e0731c11a65119b7372dbe5b3a42eb9.tar.xz qemu-64407f6a9e0731c11a65119b7372dbe5b3a42eb9.zip | |
tests/tcg/xtensa: fix watchpoint test
xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't
hardcode register numbers in the test as 0 and 1, use macros that only
index valid DBREAK* registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'linux-user/syscall.c')
0 files changed, 0 insertions, 0 deletions