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author | 2024-05-02 09:55:25 -0700 | |
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committer | 2024-05-05 21:02:48 +0100 | |
commit | a859602c746baf4892cc8ca1ce003e92411d1716 (patch) | |
tree | 9128471570d1f1a49da081fc3760a002f56fe9bd /scripts/coverage/compare_gcov_json.py | |
parent | target/sparc: Fix FMUL8x16 (diff) | |
download | qemu-a859602c746baf4892cc8ca1ce003e92411d1716.tar.xz qemu-a859602c746baf4892cc8ca1ce003e92411d1716.zip |
target/sparc: Fix FMUL8x16A{U,L}
These instructions have f32 inputs, which changes the decode
of the register numbers. While we're fixing things, use a
common helper for both insns, extracting the 16-bit scalar
in tcg beforehand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240502165528.244004-5-richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'scripts/coverage/compare_gcov_json.py')
0 files changed, 0 insertions, 0 deletions