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| author |   Anup Patel <anup.patel@wdc.com> | 2022-02-04 23:16:50 +0530 |
|---|---|---|
| committer |   Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:24:19 +1000 |
| commit | d1ceff405ae476127ec805ae99afa71d095a1bd2 (patch) | |
| tree | 39efc796aad4db301df255e2cdd8bca239c2197a /scripts/qapi/commands.py | |
| parent | target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs (diff) | |
| download | qemu-d1ceff405ae476127ec805ae99afa71d095a1bd2.tar.xz qemu-d1ceff405ae476127ec805ae99afa71d095a1bd2.zip | |
target/riscv: Implement AIA xiselect and xireg CSRs
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-15-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/qapi/commands.py')
0 files changed, 0 insertions, 0 deletions