Changes to fix warning with divide by zeroamoch/my_fixes

Staging of constant propagation seems to temporarily generate
a div by zero in axis_width_conv

2 files changed, 11 insertions, 8 deletions

diff --git a/fpga/usrp3/lib/axi/axis_width_conv.v b/fpga/usrp3/lib/axi/axis_width_conv.v
index 1cc41cb65..bb8a0870b 100644
--- a/fpga/usrp3/lib/axi/axis_width_conv.v
+++ b/fpga/usrp3/lib/axi/axis_width_conv.v
@@ -130,7 +130,8 @@ module axis_width_conv #(
     end
     // x is the greatest common divisor
     // LCM = (a*b)/GCD
-    lcm = (a*b)/x;
+    if (x > 0)  lcm = (a*b)/x;
+    else        lcm = 32768;
   end
   endfunction
 
@@ -139,6 +140,11 @@ module axis_width_conv #(
   localparam integer INT_DATA_W     = INT_KEEP_W * WORD_W;
   localparam integer UPSIZE_RATIO   = INT_KEEP_W / IN_WORDS;
   localparam integer DOWNSIZE_RATIO = INT_KEEP_W / OUT_WORDS;
+  initial begin
+    if (IN_WORDS==0)       $display("Finding LCM of 0. IN_WORDS=%d",IN_WORDS);
+    if (OUT_WORDS==0)      $display("Finding LCM of 0. OUT_WORDS=%d",OUT_WORDS);  
+    if (INT_KEEP_W==32768) $display("Finding strange INT_KEEP_W=%d",INT_KEEP_W); 
+  end
 
   wire [INT_DATA_W-1:0] fifo_i_tdata, fifo_o_tdata;
   wire [INT_KEEP_W-1:0] fifo_i_tkeep, fifo_o_tkeep;
diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv
index 7a5716d9a..c2bd0c3a2 100644
--- a/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv
+++ b/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv
@@ -29,9 +29,6 @@ module axi4s_width_conv #(
    interface.master  o   // AxiStreamIf or AxiStreamPacketIf
 );
 
-  localparam IWIDTH =i.DATA_WIDTH;
-  localparam OWIDTH =o.DATA_WIDTH;
-
   `include "axi4s.vh"
   // Parameter Checks
   initial begin
@@ -85,7 +82,7 @@ module axi4s_width_conv #(
     `AXI4S_ASSIGN(o,s1)
   end
 
-  logic [IWIDTH/8-1:0] s0_tkeep;
+  logic [i.DATA_WIDTH/8-1:0] s0_tkeep;
   always_comb begin
     if (s0.TKEEP) begin
       s0_tkeep = s0.tkeep;
@@ -96,7 +93,7 @@ module axi4s_width_conv #(
     end
   end
 
-  logic [OWIDTH/8-1:0] s1_tkeep;
+  logic [o.DATA_WIDTH/8-1:0] s1_tkeep;
   logic [15:0] s1_bytes;
 
   always_comb begin
@@ -114,13 +111,13 @@ module axi4s_width_conv #(
   end
 
   logic s0_ready, s1_valid, s1_last;
-  logic [OWIDTH-1:0] s1_data;
+  logic [o.DATA_WIDTH-1:0] s1_data;
   always_comb s0.tready = s0_ready;
   always_comb s1.tvalid = s1_valid;
   always_comb s1.tlast  = s1_last;
   always_comb s1.tdata  = s1_data;
   axis_width_conv #(
-    .IN_WORDS(IWIDTH/8), .OUT_WORDS(OWIDTH/8),
+    .IN_WORDS(i.DATA_WIDTH/8), .OUT_WORDS(o.DATA_WIDTH/8),
     .SYNC_CLKS(SYNC_CLKS), .PIPELINE(PIPELINE)
   ) axis_width_conv (
     .s_axis_aclk(s0.clk), .s_axis_rst(s0.rst),