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| author |   Martin Braun <martin.braun@ettus.com> | 2019-02-27 16:39:08 -0800 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2019-03-05 21:15:47 +0100 |
| commit | 6cdac61c6fbe196cf1c99ab24f96ea8bcc2c563d (patch) | |
| tree | 6eb4b55225dc605f060c9ded8b13303d7b40b624 | |
| parent | RFNoC: Remove incorrect flush (diff) | |
| download | uhd-6cdac61c6fbe196cf1c99ab24f96ea8bcc2c563d.tar.xz uhd-6cdac61c6fbe196cf1c99ab24f96ea8bcc2c563d.zip | |
docs: n310: Add table to explain module and PCB revisions
| -rw-r--r-- | host/docs/usrp_n3xx.dox | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/host/docs/usrp_n3xx.dox b/host/docs/usrp_n3xx.dox index 5630cff40..c109fb7bb 100644 --- a/host/docs/usrp_n3xx.dox +++ b/host/docs/usrp_n3xx.dox @@ -1063,6 +1063,26 @@ Storing data on the EEPROM is done by loading a uhd::eeprom_map_t object into the property tree. On writing this property, the driver code will serialize the map into a binary representation that can be stored on the EEPROM. +\subsection n3xx_mg_revs Module and Motherboard/Daughterboard Revisions + +The N310 module consists of three PCBs: The motherboard and two daughterboards. +Every PCB has a hardware revision number. Modules are always assembled such that +the daughterboards have the same revision number. The module revision number is +derived from the combination of daughterboard and motherboard hardware +revisions. The following table explains which module revision contains which +PCB revisions: + +Module Revision | Motherboard Revision | Daughterboard Revision | Minimum UHD Version +----------------|----------------------|------------------------|-------------------- +A | D | D | 3.11.0.0 +B | F | E | 3.12.0.0 +C | G | E | 3.13.0.2 +D | H | E | 3.14.0.0 + +The module revision is printed on the sticker on the underside of an N310 module +chassis, it is contained within the part number. For example, if the sticker +says "P/N: 141064A-01L", it is a revision A module. + \subsection n3xx_mg_regmap FPGA Register Map The following tables describe how FPGA registers are mapped into the PS. |