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| author |   Volkan Öz <volkan.oez@ni.com> | 2024-01-05 17:28:23 +0100 |
|---|---|---|
| committer |   Aki Tomita <121511582+atomita-ni@users.noreply.github.com> | 2024-01-31 09:28:51 -0600 |
| commit | 73961403c269308f3b71225a3a3d55facfaabf6e (patch) | |
| tree | b06543e18b65370e331759b30c317647679d8404 | |
| parent | python: Add version API calls (diff) | |
| download | uhd-73961403c269308f3b71225a3a3d55facfaabf6e.tar.xz uhd-73961403c269308f3b71225a3a3d55facfaabf6e.zip | |
x3xx: Adding a comment that the DAC runs with an interpolation factor of 4
| -rw-r--r-- | host/lib/usrp/x300/x300_dac_ctrl.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/host/lib/usrp/x300/x300_dac_ctrl.cpp b/host/lib/usrp/x300/x300_dac_ctrl.cpp index 1254e035e..86b6e8b62 100644 --- a/host/lib/usrp/x300/x300_dac_ctrl.cpp +++ b/host/lib/usrp/x300/x300_dac_ctrl.cpp @@ -156,6 +156,8 @@ public: write_ad9146_reg(0x03, (1 << 6)); // 2s comp, i first, byte mode // Configure interpolation filters + // Both Halfband Filters are set to Mode 0 for an interpolation + // factor of 4, without frequency shift and modulation write_ad9146_reg(0x1C, 0x00); // Configure HB1 write_ad9146_reg(0x1D, 0x00); // Configure HB2 write_ad9146_reg(0x1B, 0xE4); // Bypass: Modulator, InvSinc, IQ Bal |