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| author |   Wade Fife <wade.fife@ettus.com> | 2024-03-06 11:27:18 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2024-03-15 20:05:39 -0500 |
| commit | 8f9beccebe54a21d4993f8298c184426671624b0 (patch) | |
| tree | 42e02f369db9460cfb31bd580f20fcf43908a00e | |
| parent | fpga: ci: Update n3xx BIST image cores (diff) | |
| download | uhd-8f9beccebe54a21d4993f8298c184426671624b0.tar.xz uhd-8f9beccebe54a21d4993f8298c184426671624b0.zip | |
fpga: tools: Add option to save Vivado project
| -rw-r--r-- | fpga/usrp3/tools/make/viv_design_builder.mak | 1 | ||||
| -rw-r--r-- | fpga/usrp3/tools/make/viv_preamble.mak | 9 | ||||
| -rw-r--r-- | fpga/usrp3/tools/scripts/viv_utils.tcl | 4 |
3 files changed, 13 insertions, 1 deletions
diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak index 78e49da06..cd2f0e332 100644 --- a/fpga/usrp3/tools/make/viv_design_builder.mak +++ b/fpga/usrp3/tools/make/viv_design_builder.mak @@ -25,6 +25,7 @@ BUILD_VIVADO_DESIGN = \ export VIV_TOP_MODULE=$(2); \ export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ + export VIV_SAVE=$(VIVADO_SAVE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \ export VIV_INCR_BUILD=$(INCR_BUILD); \ diff --git a/fpga/usrp3/tools/make/viv_preamble.mak b/fpga/usrp3/tools/make/viv_preamble.mak index 8469c0581..ea2bd92fd 100644 --- a/fpga/usrp3/tools/make/viv_preamble.mak +++ b/fpga/usrp3/tools/make/viv_preamble.mak @@ -53,6 +53,15 @@ VIVADO_MODE=batch endif # ------------------------------------------------------------------- +# Project mode switch. Calling with PROJECT:=1 will use Vivado project file +# ------------------------------------------------------------------- +ifeq ($(PROJECT),1) +VIVADO_PROJECT=1 +else +VIVADO_PROJECT=0 +endif + +# ------------------------------------------------------------------- # Toolchain dependency target # ------------------------------------------------------------------- .check_tool: diff --git a/fpga/usrp3/tools/scripts/viv_utils.tcl b/fpga/usrp3/tools/scripts/viv_utils.tcl index 2c3e128df..c9c022ad0 100644 --- a/fpga/usrp3/tools/scripts/viv_utils.tcl +++ b/fpga/usrp3/tools/scripts/viv_utils.tcl @@ -26,6 +26,7 @@ namespace eval ::vivado_utils { variable g_output_dir $::env(VIV_OUTPUT_DIR) variable g_source_files $::env(VIV_DESIGN_SRCS) variable g_vivado_mode $::env(VIV_MODE) + variable g_project_save $::env(VIV_SAVE) # Optional environment variables variable g_verilog_defs "" @@ -46,12 +47,13 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } { variable g_part_name variable g_output_dir variable g_source_files + variable g_project_save variable bd_files "" file delete -force $g_output_dir/build.rpt - if {$save_to_disk == 1} { + if {$save_to_disk == 1 || $g_project_save == 1} { puts "BUILDER: Creating Vivado project ${g_top_module}_project.xpr for part $g_part_name" create_project -part $g_part_name ${g_top_module}_project } else { |