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| author |   Martin Braun <martin.braun@ettus.com> | 2023-12-12 14:55:39 +0100 |
|---|---|---|
| committer |   Wade Fife <wade.fife@ettus.com> | 2023-12-13 17:28:09 -0600 |
| commit | 1944263412d329d53b32a17e9735b79e59e319d7 (patch) | |
| tree | 93e6d5140cf2ba9ccb5f8766493b61b3a0bca079 /fpga/usrp3/tools/make/viv_design_builder.mak | |
| parent | fpga: ci: Change agent pool (diff) | |
| download | uhd-1944263412d329d53b32a17e9735b79e59e319d7.tar.xz uhd-1944263412d329d53b32a17e9735b79e59e319d7.zip | |
fpga: Remove dupes from DESIGN_SRCS
In the build Makefiles, this adds a function (uniq) which removes
duplicate entries from lists. We apply this to the DESIGN_SRCS passed
to the Vivado build process. This eliminates some warnings from
duplicate source files caused by redundantly referencing source files in
the Makefiles, possibly because they are listed in more than one source
file variable.
Diffstat (limited to 'fpga/usrp3/tools/make/viv_design_builder.mak')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_design_builder.mak | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak index 3ca44b01b..9443227e4 100644 --- a/fpga/usrp3/tools/make/viv_design_builder.mak +++ b/fpga/usrp3/tools/make/viv_design_builder.mak @@ -24,7 +24,7 @@ BUILD_VIVADO_DESIGN = \ export VIV_TOP_MODULE=$(2); \ export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ - export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ + export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \ cd $(BUILD_DIR); \ $(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou @@ -49,7 +49,7 @@ CHECK_VIVADO_DESIGN = \ export VIV_TOP_MODULE=$(2); \ export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ - export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ + export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)../../"; \ cd $(BUILD_DIR); \ $(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou |