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| author |   Lars Amsel <lars.amsel@ni.com> | 2021-04-19 09:56:55 +0200 |
|---|---|---|
| committer |   Aaron Rossetto <aaron.rossetto@ni.com> | 2021-06-03 09:34:20 -0500 |
| commit | 2a5f0ea13e6d7d00798d6547e1170ff85d4aa42a (patch) | |
| tree | de74d4da8be7d9e9593d9b7ebd31ca9e88095aca /fpga | |
| parent | mpm: check-filesystem: liberalize version check (diff) | |
| download | uhd-2a5f0ea13e6d7d00798d6547e1170ff85d4aa42a.tar.xz uhd-2a5f0ea13e6d7d00798d6547e1170ff85d4aa42a.zip | |
fpga: lib: Minor cleanup of axi_lite.vh
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/lib/axi4lite_sv/axi_lite.vh | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/fpga/usrp3/lib/axi4lite_sv/axi_lite.vh b/fpga/usrp3/lib/axi4lite_sv/axi_lite.vh index a1773d4b0..afddc5873 100644 --- a/fpga/usrp3/lib/axi4lite_sv/axi_lite.vh +++ b/fpga/usrp3/lib/axi4lite_sv/axi_lite.vh @@ -1,5 +1,5 @@ // -// Copyright 2020 Ettus Research, A National Instruments Brand +// Copyright 2021 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // @@ -8,7 +8,7 @@ // //----------------------------------------------------------------------------- -// AXI4-Lite +// AXI4-Lite //----------------------------------------------------------------------------- // Macro that drives o from i for all fields. Of course ready runs in the @@ -37,6 +37,7 @@ ``I.rvalid = ``O.rvalid;\ ``O.rready = ``I.rready; +// All signals `define AXI4LITE_PORT_ASSIGN(FORMAL,ACTUAL) \ .``FORMAL``_aclk(``ACTUAL``.clk),\ .``FORMAL``_sreset(``ACTUAL``.rst),\ @@ -58,6 +59,7 @@ .``FORMAL``_wstrb(``ACTUAL``.wstrb),\ .``FORMAL``_wvalid(``ACTUAL``.wvalid), +//NR removes clock and reset `define AXI4LITE_PORT_ASSIGN_NR(FORMAL,ACTUAL) \ .``FORMAL``_araddr(``ACTUAL``.araddr),\ .``FORMAL``_arready(``ACTUAL``.arready),\ @@ -77,6 +79,25 @@ .``FORMAL``_wstrb(``ACTUAL``.wstrb),\ .``FORMAL``_wvalid(``ACTUAL``.wvalid), +//NRS removes wstrb clock and reset +`define AXI4LITE_PORT_ASSIGN_NRS(FORMAL,ACTUAL) \ + .``FORMAL``_araddr(``ACTUAL``.araddr),\ + .``FORMAL``_arready(``ACTUAL``.arready),\ + .``FORMAL``_arvalid(``ACTUAL``.arvalid),\ + .``FORMAL``_awaddr(``ACTUAL``.awaddr),\ + .``FORMAL``_awready(``ACTUAL``.awready),\ + .``FORMAL``_awvalid(``ACTUAL``.awvalid),\ + .``FORMAL``_bready(``ACTUAL``.bready),\ + .``FORMAL``_bresp(``ACTUAL``.bresp[1:0]),\ + .``FORMAL``_bvalid(``ACTUAL``.bvalid),\ + .``FORMAL``_rdata(``ACTUAL``.rdata),\ + .``FORMAL``_rready(``ACTUAL``.rready),\ + .``FORMAL``_rresp(``ACTUAL``.rresp[1:0]),\ + .``FORMAL``_rvalid(``ACTUAL``.rvalid),\ + .``FORMAL``_wdata(``ACTUAL``.wdata),\ + .``FORMAL``_wready(``ACTUAL``.wready),\ + .``FORMAL``_wvalid(``ACTUAL``.wvalid), + `define AXI4LITE_DEBUG_ASSIGN(O,I) \ (* mark_debug = "true" *) logic [``I.ADDR_WIDTH-1:0] ``I``_debug_awaddr;\ (* mark_debug = "true" *) logic ``I``_debug_awvalid;\ |