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| author |   Wade Fife <wade.fife@ettus.com> | 2021-02-15 17:13:42 -0600 |
|---|---|---|
| committer |   Aaron Rossetto <aaron.rossetto@ni.com> | 2021-06-03 11:26:54 -0500 |
| commit | f6f43baa0012a24ed5a8cdf49240e0cb4a1f7d04 (patch) | |
| tree | 5c64535825a2bcdbdebc85fe4cb4fac0039fa7e7 /fpga | |
| parent | fpga: lib: Add AXI4 (full) interface (diff) | |
| download | uhd-f6f43baa0012a24ed5a8cdf49240e0cb4a1f7d04.tar.xz uhd-f6f43baa0012a24ed5a8cdf49240e0cb4a1f7d04.zip | |
fpga: lib: Add PHASE parameter to sim_clk_gen
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/sim/rfnoc/sim_clock_gen.sv | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv b/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv index ce7d4880a..fbe6497f6 100644 --- a/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv +++ b/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv @@ -15,7 +15,8 @@ module sim_clock_gen #( parameter realtime PERIOD = 10.0, // Period in ns parameter real DUTY_CYCLE = 0.5, // Duty cycle, in the range (0.0, 1.0) - parameter bit AUTOSTART = 1 // Start clock automatically at time 0 + parameter bit AUTOSTART = 1, // Start clock automatically at time 0 + parameter realtime PHASE = 0.0 // Phase offset ) ( output bit clk, output bit rst @@ -112,6 +113,7 @@ module sim_clock_gen #( //-------------------------- initial begin : clock_block + if (PHASE != 0.0) #(PHASE); // Toggle the clock in a loop forever begin : clock_loop #(low_time); |