diff options
| author |   Martin Braun <martin.braun@ettus.com> | 2023-07-03 11:53:37 +0200 |
|---|---|---|
| committer |   michael-west <michael.west@ettus.com> | 2023-07-07 12:35:55 -0700 |
| commit | 55379ae7fe02920780fa2ed482a7e2e6e1669529 (patch) | |
| tree | 07ef3c43f25a5964e58bbcc720c4d7d5eb2e1bc9 /mpm | |
| parent | mpm: x4xx: add intermediate clocking setting (diff) | |
| download | uhd-55379ae7fe02920780fa2ed482a7e2e6e1669529.tar.xz uhd-55379ae7fe02920780fa2ed482a7e2e6e1669529.zip | |
mpm: x440: Move clock info logging out of policy
The logging of the final clock settings object is moved into
X4xxClockManager so that no intermediate clock objects are logged.
Diffstat (limited to 'mpm')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/x4xx_clock_mgr.py | 6 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py | 4 |
2 files changed, 6 insertions, 4 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/x4xx_clock_mgr.py b/mpm/python/usrp_mpm/periph_manager/x4xx_clock_mgr.py index fec2fa68f..8d3561a3b 100644 --- a/mpm/python/usrp_mpm/periph_manager/x4xx_clock_mgr.py +++ b/mpm/python/usrp_mpm/periph_manager/x4xx_clock_mgr.py @@ -685,6 +685,12 @@ class X4xxClockManager: master_clock_rates = self.clk_policy.coerce_mcr(master_clock_rates) clk_settings = self.clk_policy.get_config( self.get_ref_clock_freq(), master_clock_rates) + self.log.debug(f"Clock Config: {clk_settings}") + self.log.info(f"Using Clock Configuration:\n" + f"DB0: Master Clock Rate: {master_clock_rates[0]/1e6} MSps " + f"@Converter Rate {clk_settings.rfdc_configs[0].conv_rate/1e9} GHz\n" + f"DB1: Master Clock Rate: {master_clock_rates[-1]/1e6} MSps " + f"@Converter Rate {clk_settings.rfdc_configs[1].conv_rate/1e9} GHz") self._configure_clock_chain( clk_settings, self.get_time_source(), self.get_ref_clock_freq()) # Bring RFDC out of reset, reset tiles and reconfigure RFDC diff --git a/mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py b/mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py index 628de992c..f7777b7e3 100644 --- a/mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py +++ b/mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py @@ -763,10 +763,6 @@ class X440ClockPolicy(X4xxClockPolicy): 'spll_config': SpllConfig(**spll_cfg) } - self.log.debug(f"Clock Config: {clk_config}") - self.log.info(f"Using Clock Configuration:\n" - f"DB0: Master Clock Rate: {mcrs[0]/1e6} MSps @Converter Rate {conv_rates[0]/1e9} GSps\n" - f"DB1: Master Clock Rate: {mcrs[1]/1e6} MSps @Converter Rate {conv_rates[1]/1e9} GSps") return X4xxClockConfig(**clk_config) |