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-rw-r--r--.ci/templates/tests/job-uhd-x410-hardware-tests-sdr-test0.yml7
1 files changed, 7 insertions, 0 deletions
diff --git a/.ci/templates/tests/job-uhd-x410-hardware-tests-sdr-test0.yml b/.ci/templates/tests/job-uhd-x410-hardware-tests-sdr-test0.yml
index 13e577ee9..af91d8257 100644
--- a/.ci/templates/tests/job-uhd-x410-hardware-tests-sdr-test0.yml
+++ b/.ci/templates/tests/job-uhd-x410-hardware-tests-sdr-test0.yml
@@ -6,6 +6,10 @@ parameters:
- name: uhdArtifactSource
type: string
default: current
+- name: uhdFpgaArtifactSource
+ type: string
+- name: fpga_imgs_source
+ type: string
jobs:
- template: templates/job-uhd-x4xx-hardware-tests.yml
@@ -17,6 +21,8 @@ jobs:
runDevTest: true
runSystemImageTest: true
uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
+ uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
+ fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
xilinxLocation: /opt/Xilinx/SDK/2019.1
dutMatrix:
sdr-test0-x410-0:
@@ -26,4 +32,5 @@ jobs:
dutFPGA: 'X4_200'
dutEmbeddedImagesArtifact: 'x4xx-images'
uartSerial: '2516351FE64E'
+ pytestDUT: 'x410'
pipelineAgent: sdr-test0