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-rw-r--r--fpga/usrp3/tools/make/viv_design_builder.mak2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak
index cd2f0e332..f10268124 100644
--- a/fpga/usrp3/tools/make/viv_design_builder.mak
+++ b/fpga/usrp3/tools/make/viv_design_builder.mak
@@ -30,7 +30,7 @@ BUILD_VIVADO_DESIGN = \
export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
export VIV_INCR_BUILD=$(INCR_BUILD); \
cd $(BUILD_DIR); \
- $(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
+ $(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(MAKEFILE_DIR)/dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
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