diff options
Diffstat (limited to 'fpga/usrp3/top/x400/Makefile')
| -rw-r--r-- | fpga/usrp3/top/x400/Makefile | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/fpga/usrp3/top/x400/Makefile b/fpga/usrp3/top/x400/Makefile index 1bf0d3fcd..81ea87b02 100644 --- a/fpga/usrp3/top/x400/Makefile +++ b/fpga/usrp3/top/x400/Makefile @@ -99,10 +99,12 @@ X440_1600_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_d_rfnoc_image_c # Option to stop after RTL elaboration. Use this flag as a synthesis check. ifndef TARGET - ifdef CHECK + ifeq ($(CHECK), 1) TARGET = rtl - else ifdef SYNTH + else ifeq ($(SYNTH), 1) TARGET = synth + else ifeq ($(IP_ONLY), 1) + TARGET = viv_ip else TARGET = bin endif @@ -333,6 +335,7 @@ help: ##Show this help message. ##GUI=1 Launch the build in the Vivado GUI. ##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. +##IP_ONLY=1 Launch the build but stop after IP generation. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0) ##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top) |