diff options
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/core/chdr_stream_endpoint.v | 14 | ||||
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/core/chdr_stream_output.v | 15 |
2 files changed, 22 insertions, 7 deletions
diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_stream_endpoint.v b/fpga/usrp3/lib/rfnoc/core/chdr_stream_endpoint.v index b6d47367a..e37b9a92c 100644 --- a/fpga/usrp3/lib/rfnoc/core/chdr_stream_endpoint.v +++ b/fpga/usrp3/lib/rfnoc/core/chdr_stream_endpoint.v @@ -218,11 +218,15 @@ module chdr_stream_endpoint #( // - [1]: Flush control path // * REG_OSTRM_CTRL_STATUS (Read-Write): // Control and status register for the output stream - // - [0] : Configuration start (strobe) - // - [1] : Is this transport lossy? - // - [3:2]: Payload SW buff (0=u64, 1=u32, 2=u16, 3=u8) - // - [5:4]: Metadata SW buff (0=u64, 1=u32, 2=u16, 3=u8) - // - [6] : Swap endianness + // - [0] : Configuration start (strobe) + // - [1] : Is this transport lossy? + // - [3:2] : Payload SW buff (0=u64, 1=u32, 2=u16, 3=u8) + // - [5:4] : Metadata SW buff (0=u64, 1=u32, 2=u16, 3=u8) + // - [6] : Swap endianness + // - [28:7]: <Unused> + // - [29] : Configuration is pending (read-only) + // - [30] : Configuration has failed (read-only) + // - [31] : Is flow-control enabled? (read-only) // * REG_OSTRM_DST_EPID (Write-Only): // The endpoint ID of a downstream stream endpoint // - [15:0]: Endpoint ID diff --git a/fpga/usrp3/lib/rfnoc/core/chdr_stream_output.v b/fpga/usrp3/lib/rfnoc/core/chdr_stream_output.v index c21649d44..14c9d42c3 100644 --- a/fpga/usrp3/lib/rfnoc/core/chdr_stream_output.v +++ b/fpga/usrp3/lib/rfnoc/core/chdr_stream_output.v @@ -10,7 +10,7 @@ // a downstream endpoint module (chdr_stream_input). Once // a stream is setup, the CHDR data on the axis_data port // can be sent downstream with full flow control. Stream -// status messages are recieved from the downstream node +// status messages are received from the downstream node // to update flow control state. This module has an external // configuration bus to initiate stream creation. // @@ -340,6 +340,9 @@ module chdr_stream_output #( reg [15:0] strc_seq_num = 16'd0; reg [2:0] cfg_delay = 3'd0; + reg cfg_fc_freq_bytes_nz; + reg cfg_fc_freq_pkts_nz; + always @(posedge clk) begin if (rst) begin state <= ST_PASS_DATA; @@ -348,7 +351,13 @@ module chdr_stream_output #( strc_seq_num <= 16'd0; cfg_pending <= 1'b0; cfg_failed <= 1'b0; + cfg_fc_freq_bytes_nz <= 1'bX; + cfg_fc_freq_pkts_nz <= 1'bX; end else begin + // Capture if the flow-control update frequency is 0 (never) + cfg_fc_freq_bytes_nz <= (cfg_fc_freq_bytes != 0); + cfg_fc_freq_pkts_nz <= (cfg_fc_freq_pkts != 0); + case (state) // ST_PASS_DATA @@ -431,9 +440,11 @@ module chdr_stream_output #( if (msg_o_tdata == CHDR_STRS_STATUS_OKAY) begin state <= ST_INIT_DLY; cfg_delay <= 3'd4; - fc_enabled <= 1'b1; data_seq_num <= 16'd0; strc_seq_num <= 16'd0; + // Only enable flow control if we're requesting periodic flow + // control updates. + fc_enabled <= cfg_fc_freq_bytes_nz || cfg_fc_freq_pkts_nz; end else begin state <= ST_PASS_DATA; cfg_failed <= 1'b1; |