diff options
Diffstat (limited to 'host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp')
| -rw-r--r-- | host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp | 43 |
1 files changed, 26 insertions, 17 deletions
diff --git a/host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp b/host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp index 1d7d59ffe..30c063d28 100644 --- a/host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp +++ b/host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp @@ -80,34 +80,43 @@ public: { // FBX uses a fixed low freq for both TX and RX return { - // Some conditions were considered for choosing the correct cal_freq, - // mainly using the PG269 manual as reference. These conditions ensure that - // the cal_freq or its harmonics don't interfere with the background (BG) - // calibration mechanism on the RFSoC. - // 1. In calib_mode2 the highest supported frequency is 0.4 * converter rate (fc). - // The minimum fc that X440 supports is 1GHz. So our highest cal_freq is 400MHz. + // Some conditions were considered for choosing the correct + // cal_freq, mainly using the PG269 manual as reference. These + // conditions ensure that the cal_freq or its harmonics don't + // interfere with the background (BG) calibration mechanism on + // the RFSoC. + // + // 1. In calib_mode2 the highest supported frequency is + // 0.4 * converter rate (fc). + // The minimum fc that X440 supports is 1GHz. So our highest + // cal_freq is 400MHz. // 2. We need to choose as high a cal_freq as we can // 3. The converter rate (fc) should not be a multiple of the cal_freq // 4. The converter rate (fc) / 8 should not be a multiple the cal_freq // 5. cal_freq should not be of a form k * (fc / 1024) where k = 1 to 1024 - // 6. The specified hysteresis threshold values work with the chosen cal_freq + // 6. The specified hysteresis threshold values work with the chosen + // cal_freq 397.55e6, // rx_freq 397.55e6, // tx_freq {0x7FFF, 0}, // output full scale dac mux 100, // delay - // From PG.269: "Threshold levels are set as 14-bit unsigned values, with any value - // from 0 to 16383 allowed. The maximum value, 16383 represents the absolute value of - // the full-scale input of the RF-ADC." - // X440 in loopback will usually receive a value of ~-11 dBm which translates to - // a threshold value of ~4000. The minimum value for a useful calibration is - // -40 dBFS according to Xilinx (~-46 dBm). So we pick a value in between (-20 dBm) - // to detect if anything is wrong in the signal path and translate this into the - // 14 bit dBm threshold value which is ~1465. The under value just needs to be slightly - // lower. Calculation from P_dBm to 14 bit threshold_value: + // From PG.269: "Threshold levels are set as 14-bit unsigned values, + // with any value from 0 to 16383 allowed. The maximum value, 16383 + // represents the absolute value of the full-scale input of the + // RF-ADC." + // + // X440 in loopback will usually receive a value of ~-11 dBm which + // translates to a threshold value of ~4000. The minimum value for + // a useful calibration is -40 dBFS according to Xilinx (~-46 dBm). + // So we pick a value in between (-20 dBm) to detect if anything is + // wrong in the signal path and translate this into the 14 bit dBm + // threshold value which is ~1465. The 'under' value just needs to be + // slightly lower. Calculation from P_dBm to 14 bit threshold_value: + // // P_rms = math.pow(10,(P_dBm-30)/10) // u_peak_to_peak = 2 * math.sqrt(P_rms * 100 * 2) # 100 Ohm Differential // # 14 bits threshold, full scale of ADC 1 Vppd ≙ 1 dBm (DS.926): - // threshold_value = u_peak_to_peak * math.pow(2,14) + // threshold_value = u_peak_to_peak * math.pow(2, 14) 1365, // under 1465, // over "calib_mode2", |