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* fpga: rfnoc: Add EOB to source port of null_src_sink blockFrancisco Salomon2024-03-122-5/+22
* fpga: Replace references to python -> python3Martin Braun2023-12-051-1/+1
* fpga: lib: Add default wiretypes to synchronizerMartin Braun2023-11-142-8/+16
* fpga: lib: Allow buffering in eth_ipv4_chdr_adapterWade Fife2023-10-181-2/+6
* fpga: rfnoc: radio: Add clock index parametersMartin Braun2023-10-172-12/+26
* fpga: rfnoc: Add clock info to backend ifcMartin Braun2023-10-172-2/+19
* fpga: Add X440/FBX supportJavier Valenzuela2023-06-124-49/+67
* fpga: lib: Fix IPv4 CHDR TUSER widthWade Fife2023-06-111-2/+2
* fpga: lib: Fix Vivado warningsWade Fife2023-06-099-14/+19
* fpga: lib: Add ctrl_port_to_wb_i2c moduleRyan Marlow2023-05-256-0/+1430
* FPGA: Add time changed pulse to timekeepermichael-west2023-05-101-2/+7
* Replay buffered TX streamer: Fix gaps in TXmichael-west2023-04-062-6/+19
* fpga: lib: Add clock_div moduleRyan Marlow2023-04-052-0/+54
* fpga: rfnoc: Add throttle to stream endpointsWade Fife2023-03-131-4/+49
* fpga: lib: Add axis_pkt_throttle.svWade Fife2023-03-134-0/+589
* fpga: lib: rfnoc: Add resize capability to chdr_stream_endpointWade Fife2023-02-241-57/+139
* fpga: lib: rfnoc: Remove redundant packet gateWade Fife2023-02-241-1/+1
* fpga: lib: rfnoc: Make RFNoC packet gates removableWade Fife2023-02-242-38/+77
* fpga: lib: rfnoc: Support multiple port widths on crossbarWade Fife2023-02-246-273/+1270
* fpga: rfnoc: Add DEVICE_FAMILY to stream endpointWade Fife2023-02-132-2/+7
* fpga: rfnoc: Add ULTRASCALE to chdr_ingress_fifoWade Fife2023-02-131-9/+10
* fpga: Update copyrightmichael-west2023-01-194-0/+4
* FPGA: Fix overflows in DDCmichael-west2023-01-191-12/+54
* FPGA: Restore FIR filter in rx_frontend_gen3michael-west2023-01-193-16/+70
* FPGA: Fix warnings in dds_freq_tune modulemichael-west2023-01-191-1/+3
* fpga: rfnoc: Add align_samples testbenchLarissa Phillip2023-01-123-0/+513
* fpga: lib: Add verilog-compatible wrapper for eth_ipv4_chdr_adapterWade Fife2023-01-102-0/+244
* fpga: lib: Add ZPU support to SV transport adapterWade Fife2023-01-105-242/+302
* fpga: lib: Fix indentation in setting_reg.vWade Fife2023-01-101-30/+35
* fpga: lib: Update header for AXI4S add/remove bytesWade Fife2023-01-102-11/+15
* fpga: rfnoc: Add timed sample alignment to radioWade Fife2022-12-194-239/+632
* fpga: lib: Add align_samples moduleWade Fife2022-12-192-0/+183
* fpga: lib: Support time and data updates in sim_radio_genWade Fife2022-12-191-69/+119
* fpga: Cosmetic changes to rx_frontend_gen3_tbMartin Braun2022-12-021-9/+26
* fpga: Fix overflows in quarterrate downconverterMartin Braun2022-12-021-6/+17
* fpga: lib: Fix inferred latch in ep_autonegotiationWade Fife2022-11-181-1/+2
* fpga: rfnoc: Fix inferred latch in chdr_strip_headerWade Fife2022-11-131-3/+6
* fpga: lib: Add MTU parameter to eth_internalWade Fife2022-09-011-7/+28
* fpga: lib: Add eth_ipv4_interface_tbWade Fife2022-08-293-0/+714
* fpga: lib: Add RegPort SystemVerilog interfaceWade Fife2022-08-292-0/+97
* fpga: lib: Add compat to Verilog transport adapterWade Fife2022-08-291-16/+13
* fpga: lib: Add verilog-compatible wrapper for eth_ipv4_interfaceWade Fife2022-08-292-0/+249
* fpga: lib: Add advanced features to IPv4 SV transport adapterWade Fife2022-08-294-209/+473
* fpga: lib: Add support for length in tuser in eth_ipv4_add_udpWade Fife2022-08-291-32/+48
* fpga: lib: Add chdr_strip_header moduleWade Fife2022-08-292-0/+156
* fpga: lib: Fix NODE_INST parameter in eth_internalWade Fife2022-08-292-6/+8
* fpga: lib: Add NET_CHDR_W parameter to transport adaptersWade Fife2022-08-294-54/+130
* fpga: sim: Update struct enum initializationWade Fife2022-08-253-1/+4
* fpga: lib: Fix addsub_hlsWade Fife2022-08-251-39/+40
* fpga: Use AR76780 patch for fir_compilerHumberto Jimenez2022-08-252-4/+4
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